LDPC decoding method suitable for NAND flash memory

An LDPC code and decoding technology, applied in the field of LDPC decoding, can solve problems such as short delay required and unavailability of NAND flash memory systems, and achieve the effects of dynamic balance, fast data transmission, and low computing power consumption

Active Publication Date: 2018-09-21
SHANDONG SINOCHIP SEMICON
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Problems solved by technology

However, the improved algorithm of general bit flipping requires the help of soft information such as the reliability information of the received bits, which cannot be obtained in the NAND flash memory system.
[0008] 4. The delay is required to be short, and the decoding needs to have a parallel structure

Method used

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  • LDPC decoding method suitable for NAND flash memory
  • LDPC decoding method suitable for NAND flash memory

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Embodiment Construction

[0030] The present invention will be further defined below in conjunction with the accompanying drawings and specific embodiments.

[0031] like figure 2 As shown, it is a flow chart of the LDPC decoding method suitable for NAND flash memory described in this embodiment, and the method includes the following steps:

[0032] S01), assuming that the code length of the LDPC code is N, the information bit length is K, and its check matrix H mn is an M ×N sparse matrix [h mn ], M, N, K are positive integers greater than 0, 0≤m≤M-1, 0≤n≤N-1, H mn There are γ 1s in each column, ρ 1s in each row, γ and ρ are integers greater than or equal to 0, the size of the check matrix is ​​M*N, and each row uses h 0 , h 1 , ……, h M-1 means that h j =( h j，0 , h j，1 , ……, h j（N-1）), 0≤j mn The set of columns where the 1 in the mth row is recorded as N(m)={n:h mn = 1}; the set of check equations that the nth bit participates in is the check matrix H mn The set of rows where the 1 in t...

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Abstract

The invention discloses an LDPC decoding method suitable for an NAND flash memory. The method comprises the steps of introducing a new judgment variable En, and obtaining performance superior to thatof a bit flipping algorithm on the basis of not significantly increasing the calculation amount. For a circuit of the NAND flash memory, a new error correction algorithm has the following advantages that the logic complexity is low, and a programming circuit is simple; real number operation is only needed instead of floating point operation or multiplication and division operation, and the operation power consumption is small; the new error correction algorithm is suitable for a parallel structure, and the operation time delay is low; the flipping threshold value is adjustable, and by adjusting the threshold value, the dynamic balance of time delay and error correction performance can be achieved.

Description

technical field [0001] The invention relates to an LDPC decoding method, in particular to an LDPC decoding method suitable for NAND flash memory. Background technique [0002] With the continuous development of microelectronics technology, the storage density of NAND flash memory has increased significantly, resulting in a sharp increase in bit error rate. The traditional error correction code architecture can no longer meet the error correction requirements of NAND flash memory. Low-Density-Parity-Check Code (Low-Density-Parity-Check Code, LDPC) has attracted a lot of research in recent years because of its excellent performance close to the Shannon limit and low decoding complexity, and has been adopted by 802.16e, DVBS2, digital broadcasting and other digital communication systems have been adopted one after another. In recent years, LDPC codes have also been discussed by scholars as error-correcting codes on NAND flash memory, hoping to reduce the ever-increasing data b...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10H03M13/11
CPCG06F11/1048H03M13/1148
Inventor 裴永航高美洲
Owner SHANDONG SINOCHIP SEMICON
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