19 results about "Memory compaction" patented technology

The invention discloses a three-dimensional voxel geometry collision detection method based on feature layering and multiple detection strategies, and relates to the technical field of computer graphics and game engines, the method comprises bit compression storage optimization, feature layering extraction and multiple collision detection, through the feature layering and multiple detection strategies, the unnecessary calculation amount is effectively reduced, and the detection efficiency is improved. The overall performance of the algorithm is improved, efficient memory compression is achieved while the detection precision is guaranteed, the requirement for computing resources is reduced, the technology can stably run in the resource-limited environment, unified collision detection processing of various geometries is supported, the universality and flexibility of the system are improved, and the system performance is improved. According to the method, integration and application in different application scenes are facilitated, the real-time rendering capability is optimized, the mobile terminal and the VR equipment are supported to run a complex physical simulation scene at a high frame rate, and the user experience and the interaction effect are improved.

A memory management method and module, a chip, an electronic device, and a storage medium. The memory management method comprises: scanning memory pages to which virtual addresses of a discontinuous memory mapping space are mapped to acquire a compressible memory page as a first memory page; compressing memory data in the first memory page to acquire corresponding memory compressed data; storing the memory compressed data in a data storage module, the data storage module being located in memory space outside the discontinuous memory mapping space; after storing the memory compressed data in the data storage module, releasing the first memory page; and setting the corresponding virtual address as a page fault address. The memory utilization is improved.

The invention discloses a memory compression method and device, and the method comprises the steps: determining a target compression algorithm corresponding to a to-be-compressed memory page in a plurality of compression algorithms; recording a corresponding relation between the to-be-compressed memory page and the target compression algorithm in a memory compression module; and when the memory compression module is in the first mode, obtaining a target compression algorithm according to the corresponding relationship, and performing compression processing on the to-be-compressed memory page based on the target compression algorithm.

The disclosure provides a memory compaction method, device, equipment and storage medium, the method comprises: determining a compaction target object and a compaction source object according to the use state and position of a memory block; the compaction target object comprises a scattered swapped-out memory block set, and the corresponding compaction source object comprises a cold block set adjacent to a continuous swapped-out space; the compaction target object comprises a scattered idle memory block set, and the corresponding compaction source object comprises a cold block set adjacent to a continuous idle space; in the scattered swapped-out memory block set, the number of continuous swapped-out memory blocks is less than a first threshold value; in the continuous swapped-out space, the number of continuous swapped-out memory blocks is greater than or equal to the first threshold value; in the scattered idle memory block set, the number of continuous idle memory blocks is less than a second threshold value; in the continuous idle space, the number of continuous idle memory blocks is greater than or equal to the second threshold value; and the use state of the compaction target object is replaced with the use state of the corresponding compaction source object.

Embodiments of the present application disclose a memory management method, device, electronic equipment and storage medium. The memory management method comprises: first acquiring a current memory recovery parameter, the memory recovery parameter comprising a memory recovery pressure and a CPU load; and then if the memory recovery parameter meets a preset parameter threshold, performing memory compaction on system memory. Through the above method, by comparing the memory recovery pressure and the CPU load with the preset parameter threshold, and performing memory compaction after the memory recovery pressure and the CPU load both meet the preset parameter threshold, the number of times of entering memory compaction in advance can be reduced, the timing of entering memory compaction is optimized, the probability of a process entering a slow path is reduced, the performance of the system is improved, and the deterioration effect caused by too many times of memory compaction is avoided.

A memory management method and module, a chip, an electronic device, and a storage medium. The memory management method comprises: scanning memory pages to which virtual addresses of a discontinuous memory mapping space are mapped to acquire a compressible memory page as a first memory page; compressing memory data in the first memory page to acquire corresponding memory compressed data; storing the memory compressed data in a data storage module, the data storage module being located in memory space outside the discontinuous memory mapping space; after storing the memory compressed data in the data storage module, releasing the first memory page; and setting the corresponding virtual address as a page fault address. The memory utilization is improved.

A system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: receiving a request to access data; identifying a location among a plurality of locations on a memory partition, among a plurality of memory partitions of the memory, by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.

The application discloses a memory compression management system for embedded device table storage, and has the characteristics that the system comprises an evicted page compression selector, a partition design and a repeated page filter, the evicted page compression selector uses an entropy sampling algorithm to estimate the compression rate of the evicted page and determines the compressed page, the partition design uses zRAM memory space for frequently swapped-in / swept-out pages and uses auxiliary storage space for infrequently swapped-in / swept-out pages, and the repeated page filter adds two design page tables, namely, a Swap Index Table and a Swap Page Table, to construct a Swap page index. Compared with the prior art, the application has the advantages of high memory utilization, reduced system energy consumption caused by the swap partition, reduced influence on application caused by the swap, further improved storage performance of the table storage system, relieved memory pressure of the embedded device, and good application prospect and commercial value.

A memory compaction process utilizes unused or reserved memory locations in an intermediate memory block to temporarily store data that has been read and / or corrected from a source memory block. As data may be read from the source memory block in different reading cycles, this process repeats until all of the data of the source memory block is ready to be written to a destination memory block. During a last or final reading cycle or phase, any data remaining in the source memory block is read from the source memory block and transferred to a destination memory block, along with the data that is stored in the reserved memory locations of the intermediate memory block.

This invention discloses a dynamic memory compression and layer scheduling method, system, and portable AI device based on sparse awareness. The method includes: analyzing the impact of each weight of a trained large model on accuracy, dividing it into key weights and secondary weights and performing asymmetric quantization compression; predicting the access probability of each model layer, performing a prefetch operation in parallel during the current model layer's computation to obtain the predicted subsequent model layer weights after asymmetric quantization compression; storing them in off-chip main memory and completing bus transmission in a compressed state, during which only valid weights are loaded using a pre-generated sparse mask; decompressing the data at the computation entry point; and using a sliding window strategy to dynamically manage the swapping in and out of the model layers: extracting the weight data of the subsequent model layers from the decompressed weight data and moving it into a window in the on-chip main memory, and then sending it to the physical execution engine of the large model to perform inference, thereby achieving stable operation of a large parameter model on a small-capacity memory device.

The invention provides a zswap memory compression software and hardware collaborative acceleration system and method based on IAA, and belongs to the technical field of computers. The system receives an asynchronous compression / decompression request through an IAA memory compression rear-end module, and submits the asynchronous compression / decompression request to IAA hardware or returns to a software path after load balancing; through a batch swap-out engine module, asynchronously submitting page compression tasks and waiting for recycling in batches; through an asynchronous swap-in engine module, asynchronously submitting a page decompression task and executing the page decompression task and metadata maintenance operation in parallel; and processing the current missing page in a polling mode through a dual-mode prefetching module, and asynchronously prefetching the page in an interrupt mode. According to the method, on the basis of asynchronization, batch and load balancing, the IAA memory hardware accelerator is introduced, the swap-out and swap-in synchronization path in the zswap is modified into the asynchronous path, the efficient zswap memory layering technology is achieved, and the utilization rate of memory resources in the cloud scene is further increased.

This invention provides a memory compression method, apparatus, electronic device, and storage medium based on large memory. The method includes: obtaining multiple object information and multiple first addresses from each memory object in a large memory block, wherein the multiple object information includes multiple corresponding object values; generating multiple second addresses corresponding to the multiple object information based on the multiple object values ​​and the multiple first addresses; and generating a compressed memory block based on the multiple object information and the multiple second addresses. By pointing object information with the same value but different addresses in the memory object to the same compressed information in the compressed memory, lightweight restorage of large memory is achieved through compressed memory blocks while maintaining service response speed.

The invention discloses a memory optimization method and device for a mobile application object pool and a storage medium, relates to the technical field of memory management, and discloses a memory optimization method for the mobile application object pool, which comprises the following steps: acquiring a memory utilization rate of a mobile application, and determining a memory compression level according to the memory utilization rate; calculating the memory occupation amount of a single object in the to-be-compressed object pool according to the data type of the object in the to-be-compressed object pool; according to the memory occupation amount and the memory compression level, determining a target reservation number of objects in the to-be-compressed object pool; detecting idle states of objects in the to-be-compressed object pool, and determining idle objects in the to-be-compressed object pool; and compressing the idle objects in the to-be-compressed object pool according to the target reservation quantity. According to the method, the memory usage condition is monitored, the memory occupation amount is calculated according to the object data type, the object retention number is dynamically adjusted in combination with different compression strategies, the memory release amount difference of fixed proportion compression is reduced, and the memory optimization efficiency is improved.

The invention discloses a compact method and a compact device for a Diithium signature based on sparse polynomial multiplication, and the method comprises the following steps: a signer generates each polynomial and a polynomial vector required by the Diithium signature based on a private key and a message to be signed in a memory compression and multiplexing manner; and outputting a Diithium signature based on the challenge polynomial obtained by calculation and the sum of polynomial vectors in the signature. The method is characterized in that the Dillium digital signature is calculated by using the coefficient-by-coefficient sparse polynomial multiplication, so that not only can the use of the memory space be optimized, but also the overall calculation performance can be optimized, the possibility is brought to the use of the Dillium in a low-memory environment, and the problem of serious performance loss during low-memory implementation is solved. In addition, the compact implementation can be applied to various environments such as embedded equipment, digital IC cards and the like, and has objective application prospects.

The application provides a memory allocation mechanism for reducing page migration of delay-sensitive applications, which comprises: (1) an application type classifier for distinguishing delay-sensitive applications (high priority) and other applications (low priority); (2) a memory allocation mechanism mainly comprising a delay-sensitive application page allocation mechanism and an other application page allocation mechanism; and (3) a memory compression mechanism, which can work with the memory allocation mechanism of the method to avoid the migration of delay-sensitive application pages and improve the service quality of the delay-sensitive applications when the system memory pressure is high.

A system and method for compressing and curating memory structures in a cognitive computing system. The system maintains a memory manifold that represents memories as geometric objects with a metric defining their relationships. Memory structures are evaluated using a curation functional that combines semantic utility, geometric complexity, and additional factors such as usage frequency or storage cost. A compression flow transforms memory structures by following the gradient of this functional to reduce redundancy and complexity while preserving meaning. Additional compression operations may include entropy reduction of memory bundles, pruning of geometrically unstable regions, projection between spaces of different dimensions, or evolution of the metric itself based on usage patterns. Compressed structures are validated against identity constraints maintained in a separate cognitive hierarchy before being returned to memory for future retrieval. The approach enables efficient long-term memory management in persistent cognitive architectures.

This invention discloses a high-performance memory compression system based on the QAT (QuickAssist Technology) hardware accelerator, relating to the field of memory compression. A new page-based parallel read / write framework is added to the ZRAM memory compression module, enabling ZRAM to better utilize the multi-core characteristics of the CPU and avoiding the waste of significant computer resources due to prolonged read / write blocking. The compression and decompression functions of ZRAM are offloaded to the QAT hardware, reducing CPU resource usage during compression algorithm execution, freeing up substantial computer resources, and minimizing the performance impact of the compression process on upper-layer applications.