294results about How to "Process compatible" patented technology

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.

The invention discloses a preparation method of a FinFET (Fin Field Effect Transistor) in a large-scale integration circuit. The method disclosed by the invention is a rear gate process and comprises the following steps of: carrying out primary pseudo gate photoetching and etching on a plane by utilizing STI (Shallow Trench Isolation) chemical-mechanical polishing; forming a source drain; depositing an intermediate medium layer; grinding the intermediate medium layer to reach the top of the primary pseudo gate by utilizing chemical-mechanical polishing again; removing the pseudo gate by utilizing a dry etching and wet etching combination method; re-etching an STI medium by utilizing a hard mask formed by the intermediate medium layer, thereby forming a Fin structure only on the area of a gate electrode; and finally carrying out real gate medium and gate electrode material deposition, thereby obtaining a final device structure. The method disclosed by the invention can be used for obtaining a flat gate line photoetching plane, and simultaneously avoiding the problem of gate material residues on a Fin sidewall, and in addition, the method disclosed by the invention can be used for effectively integrating a high-K metal gate process, avoiding increase in electric equivalent thickness and shift of a work function, thereby obtaining excellent device characteristics.