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294results about How to "Process compatible" patented technology

Semiconductor devices with reduced active region defects and unique contacting schemes

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.
Owner:NOBLE DEVICE TECH CORP +2

Semiconductor devices with reduced active region defects and unique contacting schemes

A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.
Owner:NOBLE DEVICE TECH CORP +1

Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit

ActiveCN102646599APhotolithographic planarizationSmall amount of etchingSemiconductor/solid-state device manufacturingSemiconductor devicesEngineeringDry etching
The invention discloses a preparation method of a FinFET (Fin Field Effect Transistor) in a large-scale integration circuit. The method disclosed by the invention is a rear gate process and comprises the following steps of: carrying out primary pseudo gate photoetching and etching on a plane by utilizing STI (Shallow Trench Isolation) chemical-mechanical polishing; forming a source drain; depositing an intermediate medium layer; grinding the intermediate medium layer to reach the top of the primary pseudo gate by utilizing chemical-mechanical polishing again; removing the pseudo gate by utilizing a dry etching and wet etching combination method; re-etching an STI medium by utilizing a hard mask formed by the intermediate medium layer, thereby forming a Fin structure only on the area of a gate electrode; and finally carrying out real gate medium and gate electrode material deposition, thereby obtaining a final device structure. The method disclosed by the invention can be used for obtaining a flat gate line photoetching plane, and simultaneously avoiding the problem of gate material residues on a Fin sidewall, and in addition, the method disclosed by the invention can be used for effectively integrating a high-K metal gate process, avoiding increase in electric equivalent thickness and shift of a work function, thereby obtaining excellent device characteristics.
Owner:PEKING UNIV

Forming method of semiconductor structure

The invention discloses a forming method of a semiconductor structure. The method comprises the following steps: providing a substrate which comprises a first region for forming a core storage circuit; orderly forming a gate electrode film and an initial hard mask film on the substrate; etching the initial hard mask film by using the first etching process, forming a first opening penetrating through the initial hard mask film in the first region; filling a sacrifice layer in the first opening; etching the sacrifice layer and the substrate at the bottom of the first opening by using the second etching process, and forming a first groove in the first region substrate; and forming a first isolation structure in the first groove. The method comprises: firstly forming the first opening penetrating through the initial hard mask film in the first region, and then filling the sacrifice layer in the first opening to form the first groove, wherien the sacrifice layer is firstly etched along the first opening and then the substrate is etched, thereby acquiring the first groove with small depth so as to reduce the depth-to-width ratio of the first groove; and the condition of forming a gap in the first isolation structure is avoided, thereby improving the forming quality of the first isolation structure, and then improving the electric property of a semiconductor device.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Composite VDMOS device possessing temperature sampling and over-temperature protection function

A composite VDMOS device possessing a temperature sampling and over-temperature protection function belongs to the power semiconductor device field. In the invention, a VDMOS device, a polysilicon thermal diode and an over-temperature protection circuit are integrated. Through using a negative temperature characteristic of forward voltage drop of the polysilicon thermal diode, the polysilicon thermal diode is made on an insulating layer of a VDMOS device surface so as to realize sampling of a VDMOS device operating temperature. Based on a temperature sampling signal of the polysilicon thermal diode, the over-temperature protection circuit carries out partial pressure to a gate input voltage Vin of the whole composite VDMOS device so as to obtain a gate control voltage VG of the VDMOS device. Therefore, the over-temperature protection can be performed to the VDMOS device, which is characterized by: when the operating temperature of the VDMOS device reaches TH, turning off the VDMOS device; when the internal temperature drops to TL after the VDMOS device is turned off, starting the VDMOS device, wherein temperature return difference can be represented as a following formula: Delta T=TH-TL. By using the composite VDMOS device of the invention, the accurate sampling and the over-temperature protection can be performed to the VDMOS device so that thermal failure of the device can be avoided and a service life of the device can be prolonged. A structure is simple and sampling accuracy is high. The device is compatible with a VDMOS device technology. The device is monolithic and has many other advantages.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

Silicon-based hybrid integrated laser array and preparation method thereof

The invention discloses a silicon-based hybrid integrated laser array and a preparation method thereof. The silicon-based hybrid integrated laser array comprises a plurality of distributed silicon-based hybrid integrated lasers in parallel integrated on an SOI substrate and an III-V semiconductor epitaxial layer. Each silicon-based hybrid integrated laser comprises: a silicon ridge waveguide; heatconducting layers located in special areas at two sides of the silicon ridge waveguide, wherein the special area is an area obtained after the SOI substrate removes a top silicon and a buried oxide layer; an intrinsic layer in a shape of a saddle and comprising a protrusion portion and a connection portion at two ends, wherein the protrusion portion at one end covers the upper portion of the heatconducting layers, the connection portion of the intrinsic layer is provided with an N-type waveguide layer, an active region and a P-type cover layer in order; an III-V waveguide formed by patterning the III-V semiconductor epitaxial layer and connected with the silicon ridge waveguide; a P-type ohmic contact layer; a P electrode; and an N electrode. The silicon-based hybrid integrated laser array is good in heat dissipation, simple and stable in preparation process, good in repeatability and low in manufacturing cost.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Semiconductor device used for SOI (silicon-on-insulator) high-voltage integrated circuit

The invention relates to a semiconductor device used for an SOI (silicon-on-insulator) high-voltage integrated circuit, belonging to the field of power semiconductor devices. The semiconductor device comprises a semiconductor substrate layer, a dielectric buried layer and a silicon top layer, wherein at least high-voltage LIGBT (lateral insulated gate bipolar transistor), NLDMOS (N-type lateral double-diffused metal-oxide semiconductor) and PLDMOS (P-type lateral double-diffused metal-oxide semiconductor) devices are integrated in the silicon top layer; the thickness of the dielectric buried layer is not more than 5 mum; the thickness of the silicon top layer is not more than 20 mum; multiple incontinuous high-concentration N<+> regions (doping concentration is not lower than 1e16e cm<-3>) are formed at the bottoms of the high-voltage devices and the silicon top layer above the surface of the dielectric buried layer; the high-voltage devices are isolated by dielectric isolation regions; low-voltage MOS (metal oxide semiconductor) devices can also be integrated in the device; the high-voltage devices and low-voltage devices are isolated by the dielectric isolation regions; and different low-voltage devices are isolated by field oxidation layers. The semiconductor device has the advantages that: because of the introduction of the multiple incontinuous high-concentration N<+> regions, the electric field of the silicon top layer is weakened and the electric field of the dielectric buried layer is enhanced at the same time, the breakdown voltage of the device is greatly improved, and the device can be applied in high-voltage integrated circuits in the automobile electronics, consumption electronics, green lighting, industrial control, power supply management, display driving and other fields.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Low divergence angle full Bragg reflector waveguide semiconductor laser array

ActiveCN102611002AHigh beam qualityHigh brightness laser outputOptical wave guidancePower flowLaser array
The invention relates to a low divergence angle full Bragg reflector waveguide semiconductor laser array, belonging to the field of the semiconductor laser. For lowering the longitudinal and transverse divergence angle, improving the beam quality of the laser and obtaining the high luminance laser output, the invention designs the low divergence angle full Bragg reflector waveguide semiconductor laser array. The array longitudinal structure comprises an N-type substrate, an N-type limiting layer, an N-type Bragg reflector waveguide, an active area, a P-type Bragg reflector waveguide, a P-type limiting layer and a P-type cap layer in turn from bottom to top. The N-type Bragg reflector waveguide and P-type Bragg reflector waveguide in the longitudinal structure are formed by respectively arranging at least one pair of high and low refractive index materials periodically. The array transverse structure comprises a current injection area and a transverse Bragg reflector waveguide set at two sides thereof. The transverse Bragg reflector waveguide set at two sides are respectively formed by arranging at least one pair of high and low ridge structures periodically. The lower ridge part is close to the current injection area. The low divergence angle full Bragg reflector waveguide semiconductor laser array realizes the high luminance laser output.
Owner:CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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