152results about How to "Improve formation quality" patented technology

The invention discloses a forming method of a semiconductor structure. The method comprises the following steps: providing a substrate which comprises a first region for forming a core storage circuit; orderly forming a gate electrode film and an initial hard mask film on the substrate; etching the initial hard mask film by using the first etching process, forming a first opening penetrating through the initial hard mask film in the first region; filling a sacrifice layer in the first opening; etching the sacrifice layer and the substrate at the bottom of the first opening by using the second etching process, and forming a first groove in the first region substrate; and forming a first isolation structure in the first groove. The method comprises: firstly forming the first opening penetrating through the initial hard mask film in the first region, and then filling the sacrifice layer in the first opening to form the first groove, wherien the sacrifice layer is firstly etched along the first opening and then the substrate is etched, thereby acquiring the first groove with small depth so as to reduce the depth-to-width ratio of the first groove; and the condition of forming a gap in the first isolation structure is avoided, thereby improving the forming quality of the first isolation structure, and then improving the electric property of a semiconductor device.

A downhole measurement tool includes at least one regular receiver and at least one reference receiver externally deployed on a tool body. The reference receiver is configured to be acoustically isolated from the borehole, for example, via an isolation structure including a high-impedance cap and a low-impedance gap. The reference receiver may be deployed in a linear array with the regular receiver(s) and may be substantially identical to the regular receiver(s) such that it has substantially the same sensitivity to tool mode signals and internal drilling noise as do the regular receivers. Received waveforms may be processed so as to remove tool mode arrivals and/or drilling noise.

The invention provides a formation method and a lithium-ion secondary battery, and relates to the technical field of lithium-ion batteries. The invention provides a formation method. The lithium-ion battery is formed through four formation stages which are sequentially carried out. The formation current of the four formation stages is gradually increased, and negative pressure extracted for four times is also linearly increased. According to the formation method, the formation quality of an SEI film can be effectively improved and the bulging rate of the lithium-ion battery is reduced, so that the comprehensive electrochemical properties of the lithium-ion battery are improved. According to the lithium-ion secondary battery, an electrolyte of the lithium-ion secondary battery is a non-aqueous system and formation treatment is carried out by using the formation method. The lithium-ion secondary battery does not easily bulge in the using process and has good comprehensive electrochemical properties.

The invention discloses a flattening method of an interlayer medium layer, comprising the following steps: proving a substrate provided with a grid structure; performing high-density plasma chemical vapor deposition on the substrate to form a first interlayer medium layer, wherein the thickness of the first interlayer medium layer is larger than the height of the grid structure; flattening the first interlayer medium layer; and performing plasma enhanced chemical vapor deposition on the substrate which is flattened to form a second interlayer medium layer. The invention also discloses a forming method of a contact hole. Due to the adoption of the flattening method of the interlayer medium layer and the forming method of the contact hole, the planeness of the interlayer medium layers in a wafer can be improved, furthermore, the forming quality and the consistency of each contact hole in the wafer are obviously improved, and the rate of finished products is improved.

The invention discloses a fuel spraying system for utilizing a heat pipe technology to extract heat vaporized diesel oil from exhaust gas. The fuel spraying system comprises a cylinder, a piston (1), a cylinder cover (4), an electric control oil sprayer (5), a gas inlet channel (2), an exhaust channel (17), a gas inlet valve (3) and an exhaust valve (14), wherein a diesel oil vaporizing sprayer (9) and a diesel oil vaporizer (24) are arranged on the cylinder cover (4); the diesel oil vaporizer (24) comprises a heat pipe (15) and a vaporizing cavity (23); the heat pipe (15) is composed of a heat pipe vaporizing section (16), a heat pipe heat-insulating section (18) and a heat pipe condensing section (20); the diesel oil vaporizer (24) is mounted on the cylinder cover (4); the heat pipe vaporizing section (16) is arranged on the exhaust channel (17); the heat pipe condensing section (20) is arranged in a vaporizing chamber (22); the heat pipe heat-insulating section (18) is arranged on the cylinder cover (4); and the electric control oil sprayer (5) is communicated with the vaporizing cavity (23). With such a structure, the fuel spraying system provided by the invention has the advantages that the structure is simple and compact, the heat of the exhaust gas is utilized to vaporize the diesel oil, the forming quality of the mixed gas in the cylinder is good, the burning efficiency is high and the effects of energy conservation and emission reduction are obvious.

A gas shower device, a device and a method for chemical vapor deposition. A gas shower device has a showerhead. The showerhead includes a center region and a periphery region surrounding the center region; the center region and periphery region of the showerhead have a plurality of second gas-outlets which are arranged in parallel; the second gas-outlets are used to output the second gas; a first gas-outlet arranged between two adjacent second gas-outlets, includes the first sub-gas-outlet located in the center region and the second sub-gas-outlet located in the periphery region; the first sub-gas-outlet and the second sub-gas-outlet are mutually isolated, the first sub-gas-outlet is used to output the first gas and the second sub-gas-outlet is used to output the second gas; a first gas channel is connected to the first sub-gas-outlet; a second gas channel is connected to the second gas-outlet and the second sub-gas-outlet. The film formation quality is improved by using the chemical vapor deposition device with the gas shower device.

The invention discloses graphene coating for corrosion prevention of a thermal power plant desulfurization chimney. The graphene coating consists of the following raw materials in parts by weight: 90 to 100 parts of film-forming resin, 0.5 to 3 parts of graphene, 0.5 to 2 parts of reinforced fibers, 10 to 20 parts of fillers, 10 to 20 parts of a curing agent, 15 to 30 parts of a diluents, 1 to 5 parts of polyacrylic acid, 1 to 5 parts of a polyethylenimin crosslinking agent, 1 to 3 parts of stearate and 2 to 6 parts of aids. By the mode of adding the raw materials, such as the reinforced fibers, the fillers, the polyethylenimin crosslinking agent and the polyacrylic acid, the defect that the existing corrosion-resistant coating has low durability and heat stability is overcome, the problem that the corrosion-resistant coating layer is easy to pollute and difficult to clean is solved, the developed graphene corrosion-resistant coating can completely adapt to the high-temperature strong-acid environment, the manufacturing process is simple, the practicability is high and the graphene coating is particularly suitable for thermal power plant desulfurization chimneys and flues.

The invention discloses a method for filling a contact hole, which includes the following steps: a silicon substrate, the surface of which has a contact hole opening, is provided; an adhere layer is formed inside the contact hole opening; the silicon wafer is processed by rapid thermal annealing; a barrier layer is formed on the adhere layer; metal is filled on the barrier layer in the contact hole opening. The filling method provided by the invention can be applied to the field of semiconductor manufacture and can solve the problem of forming the contact hole with relatively poor quality in the prior process below 0.25 micrometer through improving the process of filling the contact hole.

The present invention discloses a semiconductor structure and forming method of the semiconductor structure, the method comprises: providing a substrate, including a substrate and a fin on the substrate, wherein the substrate is formed with an interlayer dielectric layer, within the interlayer dielectric layer is formed with a gate opening exposing a portion of the substrate, and sidewall of the gate opening is formed a side wall; thinning a sidewall of the side wall that is away from a side of the substrate, wherein top of the side wall that is not thinned is at most flush with top of the fin; after the thinning process, forming a gate dielectric layer at bottom and the sidewall of the gate opening; forming an amorphous silicon layer on the gate dielectric layer; after the amorphous silicon layer is formed, annealing the substrate; and after the annealing process, removing the amorphous silicon layer. The method thins portion of height of the sidewall of the side wall that is away from the side of the substrate, and the top of the side wall which is not thinned is at most flush with the top of the fin, thereby reducing the probability of occurrence of an amorphous silicon layer residue problem after removal of the amorphous silicon layer.

Disclosed are a semiconductor structure and a formation method thereof. The formation method comprises the steps of forming a base, wherein the base comprises a substrate, a gate structure positionedon the substrate, source and drain doped regions positioned in the base on the two sides of the gate structure, and an interlayer dielectric layer positioned on the base and for covering the top of the gate structure, and the substrate comprises a first region for forming a P type device and a second region for forming an N type device; forming a first contact opening for exposing the source and drain doped regions in the interlayer dielectric layer on the two sides of the gate structure; performing a P type dopant segregated schottky doping process on the source and drain doped regions exposed from the first contact opening in the first region and the second region; forming a metal silicide layer at the bottom of the first contact opening; and forming a first contact hole inserting plug in the first contact opening. By adjusting the doping concentration of the source and drain doped regions in the second region, use of a photomask can be avoided when the P type dopant segregated schottky doping process is performed, so that lowering of the process cost is realized, and the N type device suffers from relatively low influence.

The invention discloses a control method for controlling the suede dimension of a monocrystalline silicon heterojunction solar battery cell. The method comprises the steps of conducting the damage layer removing treatment on the surface of a silicon wafer by using a strong alkaline solution; cleaning the silicon wafer by using a mixed solution of ammonia water and hydrogen peroxide; texturing by using a mixed solution of KOH/NaOH and a texturing additive so as to form pyramids on the surface of the silicon wafer, wherein the dimension of the pyramids is controlled through controlling the concentration of KOH/NaOH and the texturing time, and the concentration of KOH/NaOH and the texturing time are in directly proportional relationship with the dimension of the pyramid; cleaning the textured silicon wafer by using a mixed solution of hydrochloric acid and hydrogen peroxide; subjecting the textured silicon wafer to dehydration treatment by using a hydrofluoric acid solution, slowly pulling out the silicon wafer and drying the silicon wafer. According to the technical scheme of the invention, through controlling the concentration of KOH/NaOH, the texturing time and the texturing temperature, the range of the suede dimension can be controlled. In this way, the dimension of texturing pyramids on the silicon wafer is controlled within a certain range. Therefore, the suede uniformity of the silicon wafer is improved.

An image forming apparatus which includes a line head having a nozzle group in a two-dimensional matrix configuration, or a line head in which a plurality of head modules are joined together in a staggered matrix arrangement.

The invention discloses an adaptive wave beam formation method and an adaptive wave beam formation system. An actual input vector covariance matrix is dynamically evaluated according to cooperation communication between reception equipment and a sampling covariance matrix, a dispersion situation of characteristic values is minimized; performance of an adaptive wave beam is improved, influence of environment interference change on signal reception is reduced, and wave beam formation accuracy and wave beam formation robustness are improved. The method comprises steps that, 1), a sample is acquired through receiving end array elements, a covariance matrix of the sample data is calculated and is taken as an estimate of an interference noise addition covariance matrix; 2), an error matrix of the covariance matrix is constructed according to a reference signal sent by cooperation equipment and a pre-stored reference signal of the equipment; 3), the covariance matrix of the sample data acquired in the step 1) is dynamically adjusted by the error matrix acquired in the step 2), and the improved sample covariance matrix is acquired; 4), a diagonal loading coefficient is determined; and 5), weight vector solution is carried out by employing an IQRD-SMI algorithm based on LCMV, and adaptive wave beams are generated.

The invention discloses a forming method for metal silicide, which comprises the following steps of: providing a substrate with the surface having silicon material; forming a metal layer on the substrate; performing the first heat annealing treatment for the substrate; removing the unreacted metal layer on the substrate; forming a stress layer on the substrate; performing the second heat annealing treatment for the substrate. The forming method for metal silicide in the invention forms a low-resistance metal silicide with smooth surface and regular shape by adding the stress layer, thus improving the performance of the device and enhancing the final product rate of products.

The invention relates to a semiconductor structure and a formation method thereof. The formation method comprises the steps of providing a substrate; forming a gate dielectric layer on the substrate;forming a work function layer on the gate dielectric layer; forming a cap layer on the work function layer, wherein the cap layer comprise a Ti layer; and forming a metal layer on the cap layer, wherein the gate dielectric layer, the work function layer, the cap layer and the metal layer are used for forming a gate structure. According to the invention, the cap layer is formed o the work functionlayer before the metal layer is formed, the cap layer comprises the Ti layer, the metal layer generally contains easily diffused F ions, and the F ion is high in electronegativity and easy to be boundwith a Ti ion to form a titanium-fluorine bond. Correspondingly, the Ti ions can well adsorb the F ions. Therefore, the Ti layer can effectively play a role of preventing diffusion of the F ions, sothat the F ions are avoided from being diffused to the work function layer, and thus influences imposed on a work function value of the work function layer are avoided.

The invention discloses a masking board which comprises a light transmission substrate; the light transmission substrate is provided with at least a graphics area which can shade the exposure light; wherein, a notch of a phase shift grating is arranged on the light transmission substrate in at least a graphics area; and the notch is provided with light transmittance to the exposure light. The invention also discloses a corresponding forming method of the masking board. The application of the masking board can improve the resolution, focal depth and graphics contrast in the lithography process, and increase the process window.

The invention discloses a forming method of a shallow trench isolation structure, which comprises steps of providing a substrate with a shaped stop layer, defining a shallow trench pattern on the substrate, forming a shallow trench in the substrate with the shaped stop layer, depositing filling materials in the shallow trench and on the stop layer, flattening the substrate after the filling materials are deposited, wherein dishing of the filling materials in the shallow trench can be prevented by controlling the attitude difference between the filling materials in the shallow trench and the stop layer in the flattening process. The invention further provides a relative shallow trench isolation structure and a polishing method thereof. After utilizing the polishing method, the shallow trench isolation structure and the forming method thereof, flattening of the filling materials in the shallow trench can be maintained, and forming quality of the shallow trench isolation structure is increased.

An inkjet image forming apparatus includes: a liquid ejection head having an ejection surface in which a plurality of nozzles are arranged two-dimensionally; a scanning device which conveys at least one of the liquid ejection head and an image formation receiving medium on which liquid ejected from the plurality of nozzles is deposited, to cause relative movement between the image formation receiving medium and the liquid ejection head in a first direction; and a member which vibrates at a fixed frequency that is independent of a speed of the relative movement caused by the scanning device in such a manner that relative vibration is caused between the image formation receiving medium and the plurality of nozzles, wherein when vp represents a relative scanning speed produced by the scanning device in forming an image on the image formation receiving medium by the relative movement and droplet ejection from the liquid ejection head, fv represents the fixed frequency, and OSy represents an offset distance in the first direction of a pair of nozzles which form dots that are mutually adjacent in a second direction perpendicular to the first direction on the image formation receiving medium, of the plurality of nozzles arranged two-dimensionally, then relationship of OSy≈k×vp/fv (where k is a natural number) is satisfied.

The invention relates to a sealed bearing sealing structure shape detection method. An inlaid material is inlaid and solidified. The cross section is exposed through axial half-cutting. The mosaic material is polished and placed on a projection device for projection to acquire a CAD image. The invention further provides a sealing ring shape detection method. Axial half-cutting is carried out to form the cross section. The cross section is controlled to be fixed in an inlay mold. The inlay material is poured, inlaid, solidified and polished to acquire a sample. The sample is placed on the projection device. The cross section is projected to acquire the CAD image. According to the invention, a bearing sealing structure and a sealing ring structure can be directly recorded and observed, and the methods have the advantages of simple operation and convenient size and wear detection.

The present invention provides a semiconductor structure and a formation method thereof. The method comprises the steps of: providing a substrate and fins protruding from the substrate, wherein each fin comprises a fin first portion located at the surface of the substrate and a fin second portion located at the top portion of the fin first portion; forming first laying layers at the side walls ofthe fin first portions; forming second laying layers at the surfaces of the first laying layers and the top portions and the side walls of the fin second portions; forming isolation films covering thesecond laying layer on the substrate, wherein the top portions of the isolation films are higher than the top portions of the fins and are levelled with the top portions of the fins; removing the second laying layers and the isolation films higher than the top portions of the fin first portions, wherein the remaining isolation films form isolation layers; and forming gate oxide layers at the surfaces of the top portions and the side walls of the fins exposed on the isolation layers. In the invention, the first laying layers and the second laying layers can effectively weaken the stress applied to the side walls of the fins so as to avoid bending of the fins, and the formed process window of the isolation layers is large which facilitates improvement of the formation quality of the isolation layers.

An inkjet image forming apparatus includes: a liquid ejection head having an ejection surface in which a plurality of nozzles are arranged two-dimensionally; a scanning device which conveys at least one of the liquid ejection head and an image formation receiving medium on which liquid ejected from the plurality of nozzles is deposited, to cause relative movement between the image formation receiving medium and the liquid ejection head in a first direction; a drive force generating device which generates drive force for driving the scanning device; and a meshing transmission mechanism which transmits the drive force generated by the drive force generating device to the scanning device by a meshing mechanism, wherein: when Pv represents a spatial period obtained by converting a pitch of meshing teeth of the meshing transmission mechanism to an amount of the relative movement in the first direction on the image formation receiving medium, and when OSy represents an offset distance in the first direction of a pair of nozzles which form dots that are mutually adjacent in a second direction perpendicular to the first direction on the image formation receiving medium, of the plurality of nozzles arranged two-dimensionally, then relationship of OSy≈k×Pv (where k is a natural number) is satisfied.