32 results about "Wetting layer" patented technology

According to the adhesive film suitable for packaging the Mini / Micro LED display panel, through the semi-cured film made of the photo-thermal dual-curing composite glue, the wetting layer is formed by epoxy resin which does not participate in ultraviolet light curing in the adhesive film structure, the wettability of a film material to a substrate is improved, the filling effect of the film material to a cavity in the bottom of a chip is also improved, and the packaging quality of the chip is improved. The adhesive film is special in structure, easy to prepare and use and good in wettability to the Mini / Micro LED substrate, a chip can be embedded into the adhesive layer easily, the chip bottom filling effect is better, reliability is high, and cost is low. The problems that in the traditional adhesive film packaging process, permeability needs to be improved through a high-temperature softening adhesive layer, chip embedding is assisted, chip underfilling is carried out in advance, and reliability testing is difficult to pass are solved.

A semiconductor component includes a dielectric layer including an opening. The semiconductor component further includes a liner arranged in the opening in direct contact with the dielectric layer. The semiconductor component further includes a wetting layer arranged in the opening in direct contact with the liner. The semiconductor component further includes an interconnect structure arranged in the opening in direct contact with the wetting layer. The semiconductor component further includes a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer.

This application discloses an acceleration structure, welding process, and cooling system for a particle linear accelerator, relating to the field of particle acceleration equipment technology. The acceleration structure includes a left-shaped component and a right-shaped component, whose joint surfaces are welded together using alloy gaskets. The corresponding first and second acceleration half-cavities inside are assembled to form a complete disk-loaded acceleration cavity. A buffer gap is reserved between the mating edges of the two half-cavities. A vacuum maintenance component is provided above to extract the internal vacuum, and an radio frequency energy feeding component is provided on the outside to feed in external microwave energy. The supporting welding process employs local deposition of a metal barrier layer and a wetting layer, combined with alloy gaskets for temperature-controlled brazing, avoiding softening of the oxygen-free copper substrate during annealing. Furthermore, a semiconductor-based cooling system is provided around the acceleration structure to control heat deformation. This invention effectively avoids extrusion deformation of critical internal structures after welding, reduces the risk of high-frequency arcing, and significantly improves the integration and structural stability of the entire device.

The invention relates to the technical field of integrated circuits, in particular to an open circuit repairing method of a fine circuit board, which comprises the following steps of: A, depositing an anti-infiltration layer on the surface of the fine circuit board to be repaired to obtain a middle circuit board I; b, determining a defect area according to the open circuit position of the middle circuit board I; c, removing the anti-infiltration layer at the top of the defect area in the middle circuit board I to obtain a middle circuit board II; d, atomizing conductive slurry, and completely filling the defect area to obtain a third intermediate circuit board; and E, carrying out first sintering and second sintering on the third intermediate circuit board in sequence to finish repairing. According to the open circuit repairing method of the fine circuit board provided by the invention, on the premise of reducing raw material waste and saving raw material cost, the repairing precision and conductivity are improved, so that the defects in the prior art are overcome.

INFILTRATION OF A FIBROUS STRUCTURE COMPRISING AN ANTI-WETTING LAYER OF LIQUID SILICON The invention relates to a method for manufacturing a part made of a ceramic matrix composite material, comprising: - infiltrating a pre-densified fibrous structure (10) with a molten infiltration composition comprising silicon in order to form a ceramic matrix in a residual porosity of said pre-densified fibrous structure, said pre-densified fibrous structure comprising a pre-densification matrix comprising a first layer of silicon carbide (13), an anti-wetting layer (14) of molten silicon made of boron nitride (BN), silicon nitride (Si3N4), SiNxOy or oxide, for example silica (SiO2), alumina (Al2O3), zirconia (ZrO2) or mullite (3Al2O3.2SiO2), or a mixture of these compounds, the anti-wetting layer covering the first layer, and a fused silicon wetting layer of silicon carbide or carbon (15) covering the anti-wetting layer Figure for abstract: Fig. 1.

This disclosure presents a UBM structure, a brain-computer interface electrode, and a method. The UBM structure is used for a brain-computer interface electrode, which includes a flexible electrode layer and a flexible electrode substrate covering the flexible electrode layer. The flexible electrode substrate has an opening exposing the flexible electrode layer, and the UBM structure is disposed within the opening. The UBM structure includes: a first adhesion layer attached to the flexible electrode layer exposed at the bottom of the opening; a wetting layer attached to the adhesion layer; a second adhesion layer attached to the wetting layer; and a surface protective layer attached to the second adhesion layer. The total thickness of the UBM structure is less than or equal to 1 micrometer. The first and second adhesion layers are made of titanium, the wetting layer is made of copper or gold, and the surface protective layer is made of gold or platinum. The technical solution of this disclosure achieves multiple improvements in biocompatibility, electrical performance, mechanical reliability, and process feasibility.

The invention discloses a hexagonal phase silicon nanowire preparation method based on a gas-liquid-solid mechanism. The hexagonal phase silicon nanowire preparation method comprises the process steps of gold film deposition, chemical vapor deposition and the like. A stannic oxide precursor is introduced to participate in the growth process of the silicon nanowire by designing a self-compensation steam mechanism, and the characteristics of low melting point, low surface tension and low silicon equilibrium solid solubility of a tin element generated by disproportionation reaction of stannic oxide are utilized; on one hand, the thermodynamic driving force of hexagonal phase silicon nucleation is enhanced by dynamically improving the supersaturation degree of liquid drops, and on the other hand, the interface energy of the side wall of the nanowire is reconstructed by forming a tin wetting layer, so that the content of the hexagonal phase in the product is remarkably improved under the cooperative regulation and control of the dual action mechanism; and a simple, convenient, safe and efficient preparation way is provided for realizing the controllable growth of the high-purity hexagonal phase silicon nanowire.

The invention discloses a lead-free diode glass bulb and a preparation method thereof, belongs to the technical field of diode glass bulbs, and creatively introduces a modified bismuth phosphate complex to solve the key problems that a traditional lead-free glass bulb is prone to causing thermal damage, devitrification defects, insufficient dielectric strength, weak acid corrosion resistance and the like in the low-temperature sealing process. The components form an amorphous wetting layer at a high temperature, so that the sealing activation energy is remarkably reduced, and thermal damage is avoided while low-temperature sealing is realized; meanwhile, the dielectric density is enhanced by filling micropores with bismuth ions, and the dielectric strength and the insulation reliability are improved; the phosphorus component is combined with aluminum ions to form a passive film, so that the acid corrosion resistance is greatly enhanced; according to the present invention, the bottleneck in the prior art is broken through, the glass bulb is suitable for the severe environments such as miniaturized equipment, automotive electronics and industrial high-temperature systems, and the packaging safety, the durability and the reliability of the glass bulb are significantly improved.

The invention relates to a preparation method of a substrate integrated, self-assembled and self-aligned micro lens group, and belongs to the technical field of micro-nano processing of optical chips. According to the method, after a front epitaxial structure is completed and thinning and polishing are carried out, secondary epitaxy is carried out on the back surface of a wafer, a seed layer is manufactured, an infiltration layer and a lens layer are sequentially grown through an S-K growth method, and finally N infiltration layers and N lens layers are alternately grown on the back surface of the wafer, so that the epitaxial structure is formed; etching the formed epitaxial structure from top to bottom until the etching depth covers all the infiltration layers, and forming an etching window; only the lens layer is left in the etching window formed by corrosion and the infiltration layer around the etching window, and transparent materials are filled between the lens layer and the etching window for reinforcement. Based on S-K growth, the actual preparation of the micro lens group is completed in one step in the epitaxial growth stage, adverse factors such as errors and pollution accumulated in multiple links in the production circulation process are omitted, and the precision and the yield are fully guaranteed.

The invention discloses a liquid metal flexible conductor with a strain insensitive characteristic as well as a preparation method and application of the liquid metal flexible conductor, and relates to the technical field of flexible electronics and liquid metal composite materials. The liquid metal and the metal wetting layer are subjected to alloying reaction on a solid-liquid interface, an intermetallic compound interface layer is generated in situ, and the liquid metal is promoted to spontaneously infiltrate under normal pressure and compactly fill deep pores; meanwhile, a curable elastic high polymer material is adopted to conduct permeation packaging on the conductive composite layer, an elastomer-framework mechanical interlocking structure is formed in pores after curing, and geometric confinement and anti-shearing anchoring of the liquid metal are achieved; in the tensile deformation process, the liquid metal is subjected to fluid redistribution and passage bridging under the constraint of a pore confinement and an elastic body, so that the reconstruction of a conductive path is realized, and the strain-insensitive conductive characteristic of low resistance drift is obtained.

A process for manufacturing a part made of ceramic matrix composite material, the process including infiltrating a pre-densified fibrous structure with a molten infiltration composition including silicon, in order to form a ceramic matrix in a residual porosity of the pre-densified fibrous structure, the pre-densified fibrous structure including a pre-densification matrix including a first silicon carbide layer, a reactive layer including a reactive material that contains carbon and is capable of reacting with the silicon in the infiltration composition, the reactive layer covering the first layer, and a molten silicon wetting layer that is made of silicon carbide or carbon and covers the reactive layer.

A method of manufacturing a semiconductor package includes forming a wetting layer on a carrier substrate and forming a first opening and a second opening penetrating the wetting layer; forming a barrier layer and a seed layer on the first opening and the second opening; providing a conductive material to fill the first opening and the second opening; forming a first redistribution structure on the carrier substrate; removing the carrier substrate; mounting a semiconductor chip on the first redistribution structure; forming a molding layer on the first redistribution structure; and forming a second redistribution structure on the molding layer, in which removing the carrier substrate includes removing the barrier layer and the seed layer, the conductive material filling the first opening forms a through electrode, and the conductive material filling the second opening forms a connection pad.

The invention discloses an Al line forming method, and relates to the technical field of semiconductor devices, and the method comprises the steps: providing a wafer, forming a semiconductor device on the wafer, covering the semiconductor device with an ILD layer, and forming a groove in the ILD layer; depositing a barrier layer on the ILD layer and the surface of the groove; depositing a wetting layer on the barrier layer; cooling the wetting layer; depositing an Al layer on the wetting layer, wherein the groove is filled with the Al layer; and carrying out planarization treatment to remove the barrier layer, the wetting layer and the Al layer outside the groove. The wetting layer is deposited after the barrier layer is deposited, so that the step coverage rate of the barrier layer is improved; through cooling treatment on the wetting layer, the problem that in the follow-up Al deposition process, due to high temperature, grains are too large, and heating treatment cannot be conducted is solved, the problem that in the related technology, when shape-preserving filling is conducted, and the filling effect is not good, an Al wire may form a narrow or broken part is solved, and the yield of the Al wire is improved. And the high-quality Al line filling effect is realized while the process compatibility is maintained.

A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening through the insulating layer. The conductive structure is located in the opening of the insulating layer and includes a first barrier layer and a wetting layer. The first barrier layer is located on a sidewall of the opening of the insulating layer and defines a perforation through the first barrier layer. The wetting layer is located on the first barrier layer. A portion of the wetting layer is exposed from the perforation of the first barrier layer and the lower surface of the insulating layer to form a ball-shaped pad.

Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer including a first hole, a lower bump including a first bump portion in the first hole and a second bump portion protruding from the first bump portion to a bottom surface of the first dielectric layer, an external connection terminal on the bottom surface of the first dielectric layer and connected to the lower bump through the first hole, a wetting layer between the external connection terminal and the lower bump, and a first barrier / seed layer between the lower bump and the first dielectric layer and between the lower bump and the wetting layer.

The invention discloses a metal interconnection method and a semiconductor device, and the method comprises the steps: providing a semiconductor substrate which comprises a first metal part and a dielectric layer located on the first metal part, the dielectric layer is provided with a through hole, and the first metal part is exposed at the bottom of the through hole; depositing a self-integrated single layer covering the first metal part in the through hole; depositing a barrier layer on the hole wall of the through hole, wherein the self-integrated single layer is used for inhibiting deposition of the barrier layer on the self-integrated single layer; the self-integrated single layer is removed; depositing an infiltration layer in the through hole; forming a copper-manganese layer on the infiltration layer; and filling a second metal part in the through hole. According to the scheme, the problem that the reliability of the barrier layer is reduced due to the fact that the thickness of the lower barrier layer is reduced to reduce the contact resistance of the subsequent metal interconnection line in the metal interconnection process related to the related technology can be solved.

A coating composition for applying a very thin film coating to a substrate such as a polymeric film comprises a copolymer such as a block copolymer (BCP) that is compatible with the substrate, an alcohol solvent or solvents capable of dissolving the copolymer, a hydrolysed metal alkoxide precursor, a carboxylic acid stabiliser, and an active agent in an ionic, molecular, or small nanoparticle form. The active agent is configured to provide a functionality to the coating composition, selected from antimicrobial, antifungal, barrier, therapeutic, electrical, electronic, magnetic and optical. The composition is a sol comprising a continuous non-sedimentable / stable suspension of very small sized (of nano order) amorphous inorganic polymers in their oligomeric or polymeric state, and comprising the active agent dispersed in a hydrolysed metal alkoxide-BCP matrix. Substrates coated with very thin coatings are also provided, including coated LDPE which is activated before coating by UV / ozone, plasma or corona treatment prior to deposition of a wetting layer.

The invention discloses a diamond sheet and copper welding method, and relates to the technical field of superhard material and metal welding. The method comprises the following steps: firstly, cleaning a diamond sheet and a copper seat; then plating a nickel layer on the to-be-welded surface of the diamond sheet through a magnetron sputtering process, and embedding the diamond sheet plated with the nickel layer with a copper seat through a welding flux; and finally, the embedded body is placed in a vacuum brazing furnace, diffusion bonding is carried out under a set temperature-pressure curve, and a welding assembly is obtained. The nickel layer is introduced between the diamond and the solder, so that the problems of poor wettability and low bonding strength caused by chemical inertness of the diamond are effectively solved. The nickel layer is used as an excellent wetting layer with the welding flux, so that the bonding strength and the heat-conducting property of a welding interface are remarkably improved.

The invention belongs to the technical field of two-dimensional ferromagnetic materials, and particularly relates to a method for epitaxially preparing a wafer-level room-temperature two-dimensional ferromagnetic material on a GaAs substrate. Most existing two-dimensional ferromagnetic films are obtained through a mechanical stripping method, have the problems of uncontrollable thickness and size and the like, and are difficult to be used for spintronics devices. According to the method, an ultrahigh vacuum molecular beam epitaxial growth technology is adopted, GaAs (111) is subjected to high-temperature annealing in a tellurium atmosphere, a surface oxide layer is removed, a two-dimensional GaTe infiltration layer without dangling bonds grows, and a key foundation is laid for preparing a two-dimensional ferromagnetic Fe3GaTe2 film. In the preparation process of the Fe3GaTe2 material, the beam ratio of the three source materials of Fe, Ga and Te and the temperature of the substrate are accurately controlled, the high-quality two-dimensional room-temperature ferromagnetic Fe3GaTe2 film with the controllable number of unit cell layers is obtained, and a revolutionary material platform is provided for a room-temperature spin electronic device and a high-density storage technology.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier / seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

The invention relates to a manufacturing method of a ternary sputter coating brazing ceramic substrate, and relates to the technical field of ceramic substrate manufacturing. The method comprises the following steps: removing foreign matters attached to the surface of a ceramic substrate by adopting an ultrasonic cleaning process, polishing the ceramic substrate by adopting abrasive paper, treating oxidation and smudginess on the surface of a copper sheet by adopting a chemical deoiling and pickling process, attaching a chemical-resistant adhesive tape to a single surface of the copper sheet by using a vacuum adhesive tape pasting machine, and carrying out browning treatment. Forming a copper complex on the surface layer of the exposed copper sheet; carrying out magnetron sputtering on 100-200nm titanium on the surface of the ceramic substrate to form a wetting layer, and sputtering 100nm titanium nitride as an active reaction layer; sputtering a 300-500nm copper layer on the titanium nitride substrate to form a compact seed layer; carrying out silk-screen printing on a low-titanium solder on the sputtered ceramic substrate, then baking, and carrying out silk-screen printing on a second surface and baking; and stacking the copper sheets and the ceramic substrate, and performing vacuum brazing or nitrogen environment brazing. The method has the effect of improving the problems that cavities and other undesirable phenomena are prone to occurring on the copper-ceramic bonding interface and the peel strength is low.

The invention relates to the technical field of solar cells, and mainly provides a perovskite light absorption layer and a preparation method thereof, and a perovskite solar cell. The preparation method of the perovskite light absorption layer comprises the following steps: forming a wetting layer on a coating platform; placing a substrate on a coating platform, wherein the substrate comprises a first edge and a second edge; a wetting layer is arranged in a connecting area, connected with the second edge, on the coating platform; coating a perovskite precursor solution on the substrate in a direction from the first edge to the second edge, and enabling the perovskite precursor solution to reach the second edge and to be in contact with the wetting layer, thereby forming an initial perovskite light absorption layer on the substrate; and annealing the initial perovskite light absorption layer to form a perovskite light absorption layer. According to the technical scheme of the invention, the preparation method of the perovskite light absorption layer can improve the quality and uniformity of the perovskite light absorption layer.

The application discloses a thermal interface and a method for obtaining the same, and a method for promoting heat conduction, and belongs to the field of interface heat transfer. The thermal interface comprises a wetting layer and a liquid metal layer, the wetting layer comprises a rough surface, the wetting layer is located between a device and the liquid metal layer, and the rough surface of the wetting layer is in contact with the liquid metal layer. The wetting property between the wetting layer and the liquid metal layer is stronger than the wetting property between the surface of the device and the liquid metal layer, the rough surface of the wetting layer has a microstructure, and when the rough surface of the wetting layer is in contact with the liquid metal layer, the wetting property between the wetting layer and the liquid metal layer can be further improved through capillary effect. The wetting property between the liquid metal and the surface of the device can be effectively improved by using the thermal interface, so that the thermal interface can promote heat conduction between the device and the liquid metal layer, and can reduce the thermal resistance between the interfaces.

The present application relates to the technical field of liquid bearing, and particularly relates to a liquid metal bearing with a sealing structure, which comprises a shaft sleeve, a rotating shaft, liquid metal and a flange, the rotating shaft is rotatably assembled in the shaft sleeve, the rotating shaft and the shaft sleeve are filled with the liquid metal, and the flange is fixedly installed on the shaft sleeve and axially limits the rotating shaft. The flange and the shaft sleeve form a first sealing surface, the flange and the rotating shaft form a second sealing surface, the first sealing surface is sequentially arranged with an anti-wetting layer and a metal layer along a liquid metal leakage channel, the anti-wetting layer can effectively inhibit capillary penetration of the liquid metal along the end surface micro channel, the metal layer can react with the leaked liquid metal and realize plugging and blocking, and the second sealing surface is provided with a liquid locking structure and can hinder the liquid metal from leaking outward. The present application constructs a multi-stage composite sealing system on the bearing sealing interface, effectively blocks the multi-stage leakage path of the liquid metal, and is suitable for high-end precision equipment.

The present invention relates to a method for preparing a substrate-integrated, self-assembled, and self-aligned microlens array, belonging to the field of micro-nano processing technology for optical chips. In the method, after completing the front epitaxial structure and thinning and polishing, secondary epitaxy is performed on the back of the wafer and a seed layer is fabricated. A wetting layer and a lens layer are successively grown by the S-K growth method, and finally N wetting layers and N lens layers are alternately grown on the back of the wafer to form an epitaxial structure. The formed epitaxial structure is etched from top to bottom until the etching depth covers all the wetting layers to form an etching window. The wetting layers inside and around the formed etching window are etched away, leaving only the lens layers, and a transparent material is filled between them for reinforcement. Based on the S-K growth, the actual preparation of the microlens array is achieved in one step during the epitaxial growth stage, eliminating the adverse factors such as errors and contamination accumulated in multiple links during the production process, and fully ensuring the accuracy and yield.

The invention provides a UBM structure, a brain-computer interface electrode and a method. The UBM structure is used for a brain-computer interface electrode, the brain-computer interface electrode comprises a flexible electrode layer and a flexible electrode substrate wrapping the flexible electrode layer, the flexible electrode substrate is provided with an opening exposing the flexible electrode layer, the UBM structure is arranged in the opening, and the UBM structure comprises a first adhesion layer, a second adhesion layer and a third adhesion layer, the flexible electrode layer is attached to the flexible electrode layer exposed at the bottom of the opening; the wetting layer is attached to the adhesion layer; the second adhesion layer is adhered to the wetting layer; the surface protection layer is attached to the second adhesion layer; wherein the total thickness of the UBM structure is smaller than or equal to 1 micrometer, the first adhesion layer and the second adhesion layer are made of titanium, the wetting layer is made of copper or gold, and the surface protection layer is made of gold or platinum. According to the technical scheme, multiple improvements of biocompatibility, electrical properties, mechanical reliability and process feasibility are achieved.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier / seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

A transparent substrate coated with a stack of thin layers includes, from the substrate, a bottom dielectric coating including a wetting layer, which is, for example, a ZnO-based layer, a silver-based functional metal layer and a top dielectric coating, each dielectric coating including several dielectric layers, wherein the bottom dielectric coating includes a series of at least three dielectric layers having increasing refractive indices, the index difference between the three layers being at least 0.15; the top dielectric coating including a series of at least two layers having decreasing refractive indices. The Ug coefficient is kept at low values (from 0.22 to 0.31 Btu / hft2F) whereas the solar factor SHGC is maximized (from 0.720 to 0.757).

A method comprising the steps of: a) providing a first substrate (111) covered by a first bead (121), the first bead (121) comprising a first element, b) providing a second substrate (112) covered by a second bead (122), the second bead (122) comprising a second element, c) contacting the first bead (121) and the second bead (122) and heat treating to form a eutectic phase bonding the first element and the second element, the first substrate (111) is sealed to the second substrate (112), whereby a bond bead (123) based on the eutectic alloy is formed, and the first substrate (111) is sealed to the second substrate (112), the formation of the eutectic phase being accompanied by the formation of a cast portion (123 '), at least one of the first substrate (111) and / or the second substrate (112) being partially covered by a wetting layer (130), whereby during step c) the cast portion (123') of the eutectic alloy is formed on the wetting layer (130).