64 results about "Indium bump" patented technology

A hybrid image sensor includes an infrared detector array and a CMOS readout integrated circuit (ROIC). The CMOS ROIC is coupled to at least one detector of the IR detector array, e.g., via indium bump bonding. Each pixel of the CMOS ROIC includes a first, relatively lower gain, wide dynamic range amplifier circuit which is optimized for a linear response to high light level input signals from the IR detector. Each pixel also includes a second, relatively higher gain, lower dynamic range amplifier circuit which is optimized to provide a high signal to noise ratio for low light level input signals from the IR detector (or from a second IR detector). A first output select circuit is provided for directing the output of the first circuit to a first output multiplexer. A second output select circuit is provided for directing the output of the second circuit to a second output multiplexer. Thus, separate outputs of the first and second circuits are provided for each of the individual pixel sensors of the CMOS imaging array.

A process for removing indium oxide from indium bumps in a flip-chip structure to reduce contact resistance, by a multi-step plasma treatment. A first plasma treatment of the indium bumps with an argon, methane and hydrogen plasma reduces indium oxide, and a second plasma treatment with an argon and hydrogen plasma removes residual organics. The multi-step plasma process for removing indium oxide from the indium bumps is more effective in reducing the oxide, and yet does not require the use of halogens, does not change the bump morphology, does not attack the bond pad material or under-bump metallization layers, and creates no new mechanisms for open circuits.

The invention relates to an indium bump device structure and a preparation method for the same and belongs to the technical field of preparation of indium bump devices. The device structure comprises a semiconductor substrate, a welding disk, a first passivation layer, a second passivation layer, a UBM metal layer and an indium bump, wherein the UBM metal layer comprises an adhesion layer, a blocking layer, a buffer layer and a wetting layer; and in the device structure, a part of the first passivation layer is covered by the adhesion layer, and a part of the adhesion layer is covered by the second passivation layer. High structural intensity is provided by the stacking structure, so that the structure composed of the indium bump and the UBM is prevented from being separated along an interface of the adhesion layer and the first passivation layer under effects of thermal stress when the device surfers from thermal shocks. In addition, internal stress changes between the substrate and the UBM during backflow are mitigated by setting of the buffer layer, so that the indium bump is prevented from being separated from the wetting layer under too large internal stress changes. Hence, the device structure provided by the invention has higher stability and a longer service life.

A thin, flexible microelectronic assembly using thinned die (5-10 microns and lower) produced by growing a 1 μm-10 μm silicon epitaxial (Epi) layer on an oxidized silicon carrier. The integrated circuit process takes place in the standard manner in the Epi layer. The oxide layer and the silicon carrier serve as the backside handle. Once processed, the wafer can be bumped and singulated just like a normal chip without the need for the extra handle attachment processes or the backside thinning operation. Once the integrated circuits are flipped and solder reflowed to a substrate, the handle can be removed by etching the oxide. In one assembly embodiment, wells are etched in the flexible circuit board material to allow the interconnect to be recessed below the circuit board surface. An adhesive can then be placed on the board surface, locking the die to the flexible substrate. Alternatively, a nanowire interposer can be sandwiched between a bumped multilayer substrate and a bumped thin die. Further, indium bumps can be substituted for solder bumps to provide a more flexible assembly.

The invention discloses a method for preparing indium bumps of a reading circuit of an infrared detector. The method comprises steps of covering photoresist on a part, which does not need to be provided with indium bumps, of the reading circuit through the photoetching process; evaporating metal indium on a surface of the reading circuit with the photoresist according to the required thickness through the thermal evaporation process; covering photoresist on the part of the reading circuit, which needs to be provided with the indium bumps, through the photoetching process; through the ion etching process, etching the indium metal layer and the reading circuit by using argon ions while keeping the preset temperature condition, and removing the metal indium which is not protected by the photoresist; and removing the photoresist on the reading circuit, and shrinking the metal indium into a sphere to finish preparation of the indium bumps of the reading circuit.

The present invention discloses an indium bump and a preparation method thereof. The preparation method comprises the steps of A, coating a photoresist layer (20) on a chip (10); B, forming a deposition hole (21) on the photoresist layer (20); C, depositing the metal and the indium orderly, forming a bottom metal layer (30) and an indium layer (41) on the photoresist layer (20) orderly, and forming the bottom metal layer (30) and an indium bump (42) in the deposition hole (21) orderly; D, removing the photoresist layer (20) and the bottom metal layer (30) and the indium layer (41) which are located on the photoresist layer (20). The preparation method enables the process time of the indium bump preparation to be shortened and the working efficiency and the indium bump yield to be improved, at the same time, can avoid the fragmentation of the fragile samples, such as the gallium arsenide, etc., in a device. The present invention also discloses the application of the indium bump prepared according to the preparation method in an infrared focal plane array detector, the indium bump can avoid the problems, such as the pixel short circuit caused by a wet stripping technology, etc., and enables the performance of the device to be improved.

The invention discloses a focal plane array detector and a preparation method thereof. The focal plane array detector comprises an epitaxial layer. The lower surface of the epitaxial layer is providedwith multiple concave first doped regions. The interfaces of the epitaxial layer and the first doped regions are first PN junctions. A pixel element hole is arranged between the adjacent first PN junctions. The lower surface of the epitaxial layer is covered by a first passivation film. The first passivation film arranged on the surface of the first doped regions is provided with first contact holes. The exact middle of the first passivation film arranged on the surface of the pixel element holes is provided with second contact holes. The first contact holes and the second contact holes are filled with first indium bumps and second indium bumps respectively. The first indium bumps and the second indium bumps protrude out of the epitaxial layer. The upper surface of the epitaxial layer isprovided with multiple concave second doped regions. The first doped regions and the second indium bumps are connected in a one-to-one correspondence way. The objective of the invention is to solve the technical problems of crosstalk of the PN junctions of the adjacent pixel elements and small effective utilization area of the pixel elements.

The invention discloses a field emission electrode. The field emission electrode comprises a substrate and a metal electrode layer formed on the substrate, the metal electrode layer is provided with aplurality of indium bumps arranged in an array, and the top surface of each indium bump is provided with a plurality of nanowires. The preparation method comprises the steps of: S10, providing a substrate, and performing depositing on the substrate to form a metal electrode layer; S20, preparing a photoresist mask having a hole array on the metal electrode layer; S30, depositing indium materialson the photoresist mask to peel off the photoresist mask to obtain the indium bumps arranged in the array; and S40, putting the substrate with the formed indium bumps in a reaction furnace, wherein the top surface of each indium bump grows and forms the plurality of nanowires. The field emission electrode has an excellent field emission performance and is simple in preparation process, the growthof the nanowires can be performed in the low temperature and the low voltage, the growth condition is simple and gentle and easy to control, and therefore, the quality of products can be effectively improved and the production cost is reduced.

A method, apparatus, system, and device provide the ability to form one or more solder bumps on one or more materials. The solder bumps are reflowed. During the reflowing, the solder bumps are monitored in real time. The reflow is controlled in real time, thereby controlling a morphology of each of the solder bumps. Further, the wetting of the solder bumps to a surface of the materials is controlled in real time.

An indium antimonide infrared focal plane array detector chip, which includes an antireflection film [6], a low-temperature glue [7], an indium antimonide photosensitive array [8], a silicon readout circuit [9], and an indium column [10] , InSb substrate [11]. Wherein, the indium antimonide photosensitive array [8] is provided with an antireflection film [6] on the back, and an indium pillar [10] is provided on the front. The other end of the indium column [10] is connected to the silicon readout circuit [9], and the backside of the silicon readout circuit [9] is provided with an indium antimonide substrate [11], and the indium antimonide photosensitive array [8], the silicon A low-temperature glue [7] is arranged in the gap between the readout circuit [9] and the indium column [10]. The indium antimonide infrared focal plane array detector chip of the invention achieves thermal matching with the indium antimonide photosensitive array and the silicon readout circuit, reduces strain, and makes the indium antimonide infrared focal plane array detector have higher reliability. In addition, the invention provides a method for manufacturing the indium antimonide infrared focal plane array detector chip.

The invention discloses a low-damage buried mercury cadmium telluride detector chip, the chip comprises a substrate, a mercury cadmium telluride p-type epitaxial thin film, an ion implantation n-type region, a passivation layer, an n-type region electrode, a p-type electrode and an indium bump array, and the invention relates to the technology of photoelectric detector. According to the invention, a structure scheme of p-n node being prepared in a mercury cadmium telluride material etch pit is adopted, so that the position of the node region is far away from the material surface, problems including detector performance reduction, blind pixels increasing and the like caused by defects increasing caused by the acting force of a photosensitive element region form technologies such as cleaning, adhesive removing and the like are avoided. The chip has a great help to reduce blind pixel ratio of a mercury cadmium telluride plane.

The invention discloses a method for preparing a large-scale small-pixel indium gallium arsenide focal plane detector. The method comprises the specific steps as follows: 1) depositing a silicon nitride diffusion mask, 2) opening a diffusion window, 3) performing closing-tube diffusion, 4) growing a P electrode, 5) performing rapid thermal annealing, 6) opening an N groove, 7) depositing the silicon nitride passivation film, 8) opening P and N electrode holes, 9) growing a thickened electrode, 10) metallizing, and 11) growing an indium bump. The invention has the advantages that: 1, the preparation process is simpler, and the technique of first growing the P-region electrode is used to reduce the risk of conduction between the P-region electrode and the N-region InP material caused by lithography deviation and over-etching; 2, the inductively coupled plasma chemical vapor deposition (ICPCVD) technology is used to grow the low-temperature silicon nitride passivation film, and the surface passivation layer of the chip is dense, which reduces the damage caused by the process to the surface of the material and improves the surface passivation effect; and 3, the lithographic growth technique is adopted for the metalized region and the indium bump region to reduce the contact resistance of the device.

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

A process of making efficient metal bump bonding with relative low temperature, preferably lower than the melting point of Indium, is described. To obtaining a lower processing temperature (preferred embodiments have a melting point of <100° C.), a metal or alloy layer is deposited on the indium bump surface. Preferably, the material is chosen such that the metal or alloy forms a passivation layer that is more resistant to oxidation than the underlying indium material. The passivation material is also preferably chosen to form a low melting temperature alloy with indium at the indium bump surface. This is typically accomplished by diffusion of the passivation material into the indium to form a diffusion layer alloy. Various metals, including Ga, Bi, Sn, Pb and Cd, that can be used to form a binary to quaternary low melting point alloy with indium. In addition, diffusion of metal such as Sn, Sn—Zn into Ga—In alloy; Sn, Cd, Pb—Sn into Bi—In alloy; Cd, Zn, Pb, Pb—Cd into Sn—In alloy can help adjust the melting point of the alloy.

The invention discloses a two-step flip chip bonding technique of a focal-plane detector. The two-step flip chip bonding technique of the focal-plane detector comprises the steps that a photosensitivechip and a reading circuit are interconnected preliminarily through a meltback welding technology; then a high-flatness material is adopted as a flip chip bonding transitional structure; and throughsecondary cold pressure welding of the flip chip bonding transitional structure and a preliminarily-interconnected focal-plane module, the photosensitive chip and the reading circuit are completely interconnected. According to the two-step flip chip bonding technique of the focal-plane detector, the meltback welding technology and the cold pressure welding technology are organically integrated; full play is given to advantages of the two technologies; flip chip bonding random shifting is reduced, and meanwhile, the problem of dis-interconnection caused by chip flatness and the indium bump quality is solved; thus the connectivity rate and the flip chip bonding finished product rate of a large-scale high-density focal-plane detector are effectively improved; and the technique is not limitedby array scales or pixel sizes and can be conveniently applied to various area array devices.