10 results about "Bump bonding" patented technology

The invention discloses an OFPGA chip packaging structure, which comprises an OFPGA silicon chip main body and a glass substrate, TGV through holes, fine pitch waveguides and coupling gratings are arranged on the glass substrate, and the OFPGA silicon chip main body and the glass substrate are bonded through micro salient points and covalent bonds to realize mechanical fixation and signal interconnection; the glass substrate realizes vertical electrical interconnection through high-density TGV through holes, optical signal transmission is realized through fine-pitch waveguides and coupling gratings, and the micro convex points are metal convex structures formed on the glass substrate. The space utilization rate is greatly increased; ultra-short-distance electric signal transmission in the vertical direction is achieved through the high-density TGV through holes, and signal delay is greatly reduced; the thermal stress after bonding is effectively reduced by means of the similar thermal expansion coefficient characteristic of the glass substrate and the silicon chip, and the stability of photoelectric signal separation transmission is ensured by combining high-precision matching interconnection of the TGV through holes and the micro convex points.

The present invention provides an elastic wave device with improved heat dissipation, superior adhesion between the sealing portion and the wiring board, and controlled amount of sealing resin that penetrates between the wiring board and the device chip. [Solution] The elastic wave device comprises a wiring board 3, a device chip 5 having a resonator and flip-chip bonded to the wiring board 3 via a plurality of bumps, a metal pattern 7 formed on the outer edge portion of the wiring board 3, a plurality of bump pads 9 formed on the wiring board 3 including an antenna pad ANT, a transmit pad Tx, a receive pad Rx, and a ground pad GND, a solder resist layer 10 formed to bond to both the metal pattern 7 and the wiring board 3, and a sealing portion made of a sealing resin formed by a thermosetting process that penetrates between the wiring board 3 and the device chip 5 to hermetically seal the device chip 5, wherein the solder resist layer 10 and the sealing portion are bonded.

The invention discloses an efficient detection method for defects of an interconnection hole chain of a micro bump bonding integrated chip. The efficient detection method mainly comprises the following steps: carrying out a direct current electrical test on the interconnection hole chain; calculating an interconnection hole chain resistance value according to a direct current test result, judging a resistance abnormal value, and picking out a short-circuit or open-circuit interconnection hole chain according to the abnormal value; cutting the whole short-circuit or open-circuit interconnection hole chain structure from the middle of the salient point through a scribing process; mounting the bonding integrated chip with the cut interconnection hole chain structure on a section polishing clamp, keeping the section flush with a polishing disc, and performing section polishing on the whole cut interconnection hole chain structure; cleaning the polished bonding integrated chip; utilizing an optical microscope to inspect the cross section of the interconnected hole chain, screening abnormal points, and utilizing SEM to detect and analyze the bonding defects of the interconnected hole chain.

The embodiment of the present disclosure provides a bump structure and a preparation method thereof. The method comprises the following steps: providing a wafer; forming a UBM layer electrically connected with a pad on the surface of the wafer; electroplating a palladium bump layer electrically connected with the pad on the UBM layer, and electroplating a copper bump layer on the palladium bump layer to form a palladium-copper bump; performing chemical plating on the surface of the palladium-copper bump to form a first protective layer wrapping the palladium-copper bump; and performing chemical plating on the surface of the first protective layer to form a second protective layer wrapping the first protective layer. The palladium bump layer and the copper bump layer are formed in sequence to form the palladium-copper bump, the palladium bump layer increases the overall bump bonding force, provides reliability and improves the overall appearance; and the first protective layer and the second protective layer realize all-around coverage of the palladium-copper bump, thereby fundamentally eliminating oxidation and significantly improving product reliability.

Fabrication of avalanche photodiodes on a first wafer for operation in Geiger mode and integration with read-out integrated circuits (ROICs), fabricated on a second wafer, are described. Photodiode arrays are fabricated using a thin epitaxial layer grown on a semiconductor-on-insulator wafer. Chips are diced from the first wafer and bump bonded to chips diced from the second wafer.

The invention relates to the technical field of semiconductors, and discloses a semiconductor packaging structure and a preparation method thereof. The first chip is positively arranged above the packaging substrate; the first chip comprises a body part located at the middle position and an edge part located at the side part; the body part protrudes out of the edge part; pins are arranged on the upper surface of the edge part; a rewiring layer is arranged in the first chip, and the pins are connected to the rewiring layer; the first chip is a silicon-based chip; the at least one second chip is arranged in an inverted manner, is positioned at the side part of the first chip and is positioned above the edge part; the projection of the second chip on the packaging substrate is partially overlapped with the edge part; a plurality of first salient points and a plurality of second salient points are arranged below the second chip; the first bumps are connected to a substrate bonding pad above the packaging substrate in a bonding manner; the second bumps are bonded to the pins. According to the invention, high-efficiency interconnection among multiple chips can be realized while the packaging integration level and reliability are improved, the silicon proportion and the supporting performance are improved, and the warping of the substrate is reduced.

A method for forming an electronic chip assembly includes bonding a first metal plate to a first surface of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend into at least the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate containing a second cavity is positioned on the second surface of the substrate over the first cavity such that the electronic component is enclosed within the first and second cavities by the first and second metal plates.

The invention discloses a photoelectric co-packaging method and a photoelectric co-packaging structure, and the method comprises the steps: S1, respectively preparing a photonic integrated circuit die, an electronic integrated circuit die and an interposer wafer, and enabling the photonic integrated circuit die to be provided with an optical connection port; s2, bonding the bare photonic integrated circuit and the bare electronic integrated circuit to the interposer wafer through the micro bumps by flip chip bonding; s3, performing plastic packaging on the bonded interposer wafer so as to provide mechanical support; s4, thinning the top of the interposer wafer after plastic package, and removing at least part of the plastic package material to expose the optical connector of the photonic integrated circuit die; step S5, cutting the thinned interposer wafer into an interposer bare wafer; and step S6, preparing a packaging substrate, and bonding the interposer bare chip to the packaging substrate through the micro bumps by flip chip bonding.

An optical module according to the disclosure includes a stem, a submount and a connection substrate provided on the stem, a laser, a modulator, a first high-frequency line, a termination resistor, and a termination resistor pattern connected to the termination resistor provided on the submount, a second high-frequency line provided on the connection substrate and configured to transmit a high-frequency signal to the first high-frequency line; a bump bond provided on a modulator electrode of the modulator; a first wire having one end connected to the first high-frequency line and a stitch as the other end provided on the bump bond, and a continuous wire connecting the first high-frequency line and the termination resistor pattern via the bump bond.

The invention provides a display semiconductor device and a preparation method thereof. The display semiconductor device comprises a driving substrate, a pixel unit and a metal bonding layer. The driving substrate is provided with a first contact; the pixel units are located above the driving substrate, and the transverse size is at least partially increased from bottom to top; the metal bonding layers are arranged on the surface of the driving substrate, are electrically connected with the first contacts, extend to the side walls of the pixel units and are electrically connected with the first semiconductor layers in a large area, and the metal bonding layers of the adjacent pixel units are mutually isolated. Through large-area contact between the metal bonding layer and the first semiconductor layer, the contact resistance is reduced, and the luminous efficiency is improved. And large-area medium-free continuous metal layer bonding is adopted, and compared with mixed bonding or salient point bonding, the difficulty of the bonding process is remarkably reduced. The metal bonding layer extends to the side wall, the heat dissipation area is increased, a three-dimensional heat diffusion path is formed, heat accumulation in the device is effectively reduced, thermal stress generated by difference of thermal expansion coefficients is reduced, the interface stripping risk is restrained, and reliability is improved.