Microbeam assembly and associated method for integrated circuit interconnection to substrates

Abstract

A microbeam interconnection method is provided to connect integrated circuit bond pads to substrate contacts. Conductive leads (microbeams) are releasably formed, by a process such as electroplating or vacuum deposition, over a release layer deposited on a ceramic, glass or similar carrier. The microbeam material adheres only very weakly to the release layer. After the inner ends of the microbeams have been bonded to IC bond pads, such as by flip chip bump bonding, and the integrated circuit has been fully tested, the IC is lifted away from the carrier, causing the microbeams to peel away from the release layer. After straightening the microbeams against a flat surface, the outer ends of the microbeams may then be bonded to contacts on an MCM or other substrate. The method permits full electrical testing at speed and high speed bonding. The method significantly reduces mechanical stresses in interconnect bonds and thereby improves integrated circuit reliability.

Description

FIELD OF THE INVENTION [0001] The present invention relates to interconnections between integrated circuits and substrates and, more particularly, to a microbeam assembly method which allows for electrical testing of an integrated circuit at speed and subsequent interconnection of the integrated circuit to a substrate. BACKGROUND OF THE INVENTION [0002] An essential step in the fabrication of microelectronic hardware is the step of providing electrical connections from the electronic devices to the interconnection board or substrate. As microelectronic devices such as integrated circuits become more highly integrated and more complex there is also great need for a method to fully functional test the device at speed before assembly into the circuit. Otherwise, large amounts of time are required to locate failed devices on a complex substrate containing several high lead count devices. For physically large devices the interconnection method must also be able to compensate for signific...

AI Technical Summary

Benefits of technology

[0014] The method and apparatus of the present invention provide an integrated circuit packaging system that reduces interconnect bond mechanical stress and thereby improves reliability without requiring solder flux. As noted above,

Problems solved by technology

Otherwise, large amounts of time are required to locate failed devices on a complex substrate containing several high lead count devices.

The bonds may fail under exposure to this repeated stress, and the reliability of the packaged integrated circuit may thereby be degraded.

TAB and other lead bonding approaches generally produce leads that extend beyond the chip footprint (such as by 40 mils), which may be a problem in applications requiring tight spacing.

In addition, the high bonding forces required to bond a copper TAB lead may damage the chip or substrate and the removal of defective TAB bonded chips from a substrate is often difficult to accomplish without damaging the substrate.

As the structure endures multiple thermal cycles during operation, the flip chip projections 44 may f

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