53 results about "Superconducting integrated circuits" patented technology

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium / aluminum oxide / niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and / or additive patterning. A superconducting metal layer may be deposited by electroplating and / or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

The invention discloses a superconducting transistor device and a preparation method thereof, and belongs to the field of superconducting electronics, and the superconducting transistor device comprises a first grid electrode and / or a second grid electrode, a superconducting nanowire, a first electrode and a second electrode. Wherein the first grid electrode and the second grid electrode are located on the two sides of the superconducting nanowire respectively, or the first grid electrode or the second grid electrode is located on the side edge of the superconducting nanowire; two ends of the superconducting nanowire are respectively connected with the first electrode and the second electrode; the first grid electrode and / or the second grid electrode, the first electrode and the second electrode are used for being connected with an external electrode. The superconducting transistor device with a logic function is obtained through construction of the superconducting nanowires and the grid electrodes, the structure of a superconducting logic circuit is simplified, the integration level and expansibility of the device are improved, the preparation difficulty and the requirement for magnetic shielding are greatly reduced, and a new technical route is provided for development of superconducting integrated circuits.

Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and / or an unexpected resistance in a superconducting resonator.

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.

A system and method are disclosed for a superconducting traveling-wave parametric amplifier (TWPA) with improved control and performance. In a preferred embodiment, the amplifier comprises an integrated array of symmetric rf-SQUIDs in a transmission line structure. A device was fabricated using niobium superconducting integrated circuits, and confirmed predicted performance, with a maximum gain up to 17 dB and a bandwidth of 4 GHz. A similar device can be applied as a low-noise, low-dissipation microwave amplifier for output from a superconducting quantum computer, or as a preamplifier, switch, or frequency converter for a sensitive microwave receiver, or as an output amplifier for a frequency-multiplexed superconducting detector array.

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A system and method for eliminating flux trapping in superconducting integrated circuits. An array of control current lines is provided, closely coupled thermally and magnetically with a superconducting integrated circuit. These control lines are configured to produce both heat and magnetic fields, with amplitudes and sequences of control currents designed to sweep magnetic flux away from the superconducting circuits at cryogenic operating temperatures. Verification may be obtained using SQUID magnetic sensors located close to the circuits. Similar methods may be applied to all superconducting integrated circuits which are sensitive to weak magnetic fields, including classical single-flux-quantum circuits, sensor arrays, and quantum computing circuits comprised of superconducting qubits. This system is scalable to superconducting circuits with up to millions of superconducting devices. The control currents may be configured to operate under automated feedback control.

Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and / or an unexpected resistance in a superconducting resonator.

In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.

Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium / aluminum oxide / niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and / or additive patterning. A superconducting metal layer may be deposited by electroplating and / or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

A method of forming a superconducting integrated circuit device, comprising providing a Josephson junction (JJ) structure disposed on a first patterned superconducting layer, wherein the first patterned superconducting layer is formed from a first superconducting material disposed on a substrate. A cap layer comprising a first component and a second component is formed over the first patterned superconducting layer.Forming the cap layer comprises forming the first component from a sacrificial material in a first region of the cap layer, the first component surrounding the JJ structure, wherein at least a portion of a top surface of the JJ structure facing away from the substrate is uncovered by the sacrificial material, and forming the second component from a first dielectric material in a second region of the cap layer different from the first region. A via is formed in the cap layer over a portion of the first patterned superconducting layer. A second patterned superconducting layer made of a second superconducting material is formed overlying the top surface of the JJ structure and the via. The sacrificial material is removed. Thus, the JJ structure is not in contact with any dielectric material, thereby reducing dielectric losses.

To provide a system and method for fabricating integrated circuits for superconducting applications.SOLUTION: A method of depositing a protective cap over a trilayer Josephson junction includes depositing a trilayer comprising a Nb / AlOx / Nb trilayer over a wafer, over a surface of a dielectric layer, or over a surface of a metal layer, patterning the trilayer by a lithographic process, pre-cleaning an exposed surface (e.g., a top surface) of the patterned trilayer, and depositing a protective cap over the trilayer. The cap comprises silicon nitride and serves to protect the tri-layer (specifically, the aluminum oxide layer) from degradation in subsequent processing.SELECTED DRAWING: Figure 6

This solves the connectivity problem between qubits. [Solution] The superconducting integrated circuit includes a first superconducting device 102 having a first superconducting loop 108 with a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device 104 having a second superconducting loop 112 with a second superconducting trace in a second layer. The first superconducting loop intersects with the second superconducting loop in an intersection region 120. At least a portion of each of the first and second superconducting traces inside the intersection region follows a detour path that is narrower than at least a portion of each of the traces outside the intersection region and inductively approaches at least a portion of the other path.

The present disclosure relates to superconducting integrated circuits and methods of manufacturing the same. A method of manufacturing a superconducting integrated circuit includes forming a first superconducting layer; forming a layer stack on the first superconducting layer, the layer stack comprising a Josephson junction (JJ) layer stack, a metal layer arranged on the JJ layer stack, and a fourth superconducting layer arranged on the metal layer, the JJ layer stack comprising a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer arranged on the second superconducting layer, and an electrically insulating barrier layer arranged between the second superconducting layer and the third superconducting layer; structuring the fourth superconducting layer, including performing a first etching process, the metal layer serving as an etch stop layer and a first portion of the metal layer being exposed; structuring the layer stack to form a JJ structure; forming a dielectric layer on the JJ structure; structuring the dielectric layer, including performing a second etching process, the metal layer serving as an etch stop layer and a second portion of the metal layer being exposed; forming a fifth superconducting layer on the structured dielectric layer, the fifth superconducting layer being electrically coupled to the third superconducting layer.

Systems and methods of the disclosed technology relate to hybrid integrated superconducting systems, superconducting components such as quantum wave shutters, quantum multiplexers, quantum wave memories and / or other disclosed aspects. In one example embodiment, a superconductor Metal-Oxide-Semiconductor (SMOS) chip is disclosed containing one or more superconducting components on a single die, wherein the one or more superconducting components may include a classical computing system or devices, a quantum computing system and / or devices that manipulate and control quantum waves, and a signal conversion subsystem that transforms signals between classical subsystems and quantum subsystems in order to establish a connection between classical and quantum information. Additional aspects relate to quantum devices and their structure(s) such as quantum wave shutters, quantum multiplexers and / or quantum wave memories, among other innovative systems, devices, features and functionality disclosed herein.

The application provides a superconducting integrated circuit with double-layer Josephson junctions and a preparation method thereof. The superconducting integrated circuit comprises a substrate, a logic layer and a signal transmission layer. The logic layer is located above the substrate and comprises at least one lower Josephson junction for storage and / or operation. The signal transmission layer is located above the logic layer and is electrically connected with the logic layer to transmit input and output signals of the logic layer. The signal transmission layer comprises at least one upper Josephson junction for a Josephson transmission line. The application adopts the double-layer Josephson junctions. The upper Josephson junctions can be configured without bias resistors and parallel resistors. The application is beneficial to improving the integration of the superconducting integrated circuit and the frequency of the superconducting integrated circuit. Smaller integration area of the Josephson transmission line makes the wiring of the upper signal transmission layer to the lower logic more flexible and free. In addition, the signal transmission layer can be used to manufacture passive transmission lines, further improving the integration of the superconducting integrated circuit.

The invention relates to a method of manufacturing a superconducting integrated circuit device. A method of manufacturing a superconducting integrated circuit device includes providing a Josephson junction (JJ) structure disposed on a first structured superconducting layer, a first superconducting material disposed on a substrate forming the first structured superconducting layer. A capping layer having a first feature and a second feature is formed over the first structured superconducting layer. Forming the capping layer includes forming a first feature surrounding a JJ structure from a sacrificial material in a first region of the capping layer, at least a portion of a top surface of the JJ structure facing away from the substrate being uncovered by the sacrificial material; a second feature is formed from the first dielectric material in a second region of the capping layer different from the first region. A via is formed in the capping layer over a portion of the first structured superconducting layer. A second structured superconducting layer of a second superconducting material is formed overlying the via hole and the top surface of the JJ structure. And removing the sacrificial material. Thus, the JJ structure is not in contact with any dielectric material, thus reducing the dielectric loss.

A method for fabricating a superconducting integrated circuit comprises: forming a first superconducting layer; forming a layer stack above the first superconducting layer, wherein the layer stack comprises: a Josephson contact (JJ) layer stack, wherein the JJ layer stack comprises: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer arranged above the second superconducting layer, and an electrically insulating barrier layer arranged between the second superconducting layer and the third superconducting layer, a metal layer arranged above the JJ layer stack, and a fourth superconducting layer arranged above the metal layer;Structuring the fourth superconducting layer, comprising performing a first etching process, wherein the metal layer serves as an etch stop layer and a first section of the metal layer is exposed; structuring the layer stack to form a JJ structure; forming a dielectric layer over the JJ structure; structuring the dielectric layer, comprising performing a second etching process, wherein the metal layer serves as an etch stop layer and a second section of the metal layer is exposed; and forming a fifth superconducting layer over the structured dielectric layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.

The invention provides a power grid model construction method and system, a simulation method, electronic equipment and a medium. The power grid model construction method comprises the steps of obtaining a power grid layer graph of a superconducting integrated circuit layout; classifying the power grid layer graph to obtain a bright field region graph and a dark field region graph; performing power grid modeling on the bright field area graph to obtain a bright field area power grid model; and performing power grid modeling on the dark field area graph to obtain a dark field area power grid model. According to the method and the device, an efficient modeling strategy is adopted, so that consumption of computing resources is effectively reduced. Besides, simulation analysis based on the model constructed by the invention can accurately describe the change of the electrical property of the superconducting active device, so that the applicability of the model is improved. In addition, the method has the capability of converting the layout design of the superconducting integrated circuit under various superconducting processes into an impedance network, and shows relatively high universality.

The invention provides a dynamic logic simulation method and system based on a superconducting integrated circuit, a terminal and a medium, and the method comprises the steps: S100, building a simulation queue based on layout information or a gate-level netlist file of the superconducting integrated circuit; step S200, acquiring an input port of the logic gate unit corresponding to the earliest signal arrival time and a corresponding excitation signal from the simulation queue; s300, determining the state change of the logic gate unit based on the input port of the logic gate unit and the corresponding excitation signal thereof and the state machine description defined in the unit library of the superconducting integrated circuit; step S400, updating the simulation queue based on the state change of the logic gate unit; and step S500, repeating the steps S200 to S400 until the simulation queue is empty or the preset maximum simulation time is reached, and ending the simulation process. According to the invention, the logic operation in the superconducting integrated circuit is simplified, the total time length of the whole waveform simulation is shortened, and the dynamic logic simulation efficiency is remarkably improved.

To provide a superconducting device capable of more accurately arranging a non-contact coupling circuit of a superconducting integrated circuit chip and a non-contact coupling circuit of a circuit board. The chip has a first electrode made of a first superconducting material and a first non-contact coupling circuit on a surface thereof. The board has a second electrode made of a second superconducting material and a second non-contact coupling circuit on a surface thereof, and is arranged to face the chip. The second electrode has a protrusion protruding toward the chip. The protrusion includes a flat upper surface. The first electrode has a flat surface and a first recess. The first recess is arranged to face the upper surface to be located inside the upper surface of the protrusion. A third superconducting material connecting the upper surface and the first recess.

The application discloses a superconducting ring spacer and a preparation method thereof, which greatly simplifies a superconducting quantum test system, is beneficial to the large-scale development of a superconducting quantum computing circuit, and realizes compatibility with a superconducting integrated circuit in a preparation process, so that the superconducting quantum test system is greatly simplified, and the large-scale development of the superconducting quantum computing circuit is facilitated.

The invention provides a Josephson junction barrier layer thickness monitoring method comprising the following steps: providing a substrate, forming a Josephson junction on one side of the substrate, the Josephson junction comprising a first superconducting material layer, a barrier layer and a second superconducting material layer which are stacked on the substrate in sequence, carrying out area division on the upper surface of the second superconducting material layer, and forming a Josephson junction barrier layer thickness on the upper surface of the second superconducting material layer; a thickness measurement area is determined, a patterned photoetching layer is formed on the second superconducting material layer, a first opening for exposing the thickness measurement area is formed in the photoetching layer, the second superconducting material layer in the thickness measurement area is etched and thinned based on the photoetching layer, and the thickness of the thinned second superconducting material layer is larger than 0 nm and smaller than 20 nm. And measuring the thickness measurement area by using an ellipsometer to obtain the thickness value of the barrier layer. According to the method for monitoring the thickness of the Josephson junction barrier layer, rapid and nondestructive measurement of the thickness and uniformity of the large-size wafer-level barrier layer is realized by using the ellipsometer, and the requirements of a large-scale high-Jc superconducting integrated circuit can be met.

Systems and methods of the disclosed technology relate to hybrid integrated superconducting systems, superconducting components such as quantum wave shutters, quantum multiplexers, quantum wave memories and / or other disclosed aspects. In one example embodiment, a superconductor Metal-Oxide-Semiconductor (SMOS) chip is disclosed containing one or more superconducting components on a single die, wherein the one or more superconducting components may include a classical computing system or devices, a quantum computing system and / or devices that manipulate and control quantum waves, and a signal conversion subsystem that transforms signals between classical subsystems and quantum subsystems in order to establish a connection between classical and quantum information. Additional aspects relate to quantum devices and their structure(s) such as quantum wave shutters, quantum multiplexers and / or quantum wave memories, among other innovative systems, devices, features and functionality disclosed herein.

Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

Systems and methods of the disclosed technology relate to hybrid integrated superconducting systems, superconducting components such as quantum wave shutters, quantum multiplexers, quantum wave memories and / or other disclosed aspects. In one example embodiment, a superconductor Metal-Oxide-Semiconductor (SMOS) chip is disclosed containing one or more superconducting components on a single die, wherein the one or more superconducting components may include a classical computing system or devices, a quantum computing system and / or devices that manipulate and control quantum waves, and a signal conversion subsystem that transforms signals between classical subsystems and quantum subsystems in order to establish a connection between classical and quantum information. Additional aspects relate to quantum devices and their structure(s) such as quantum wave shutters, quantum multiplexers and / or quantum wave memories, among other innovative systems, devices, features and functionality disclosed herein.