21 results about "Superconducting integrated circuits" patented technology

A system and method are disclosed for a superconducting traveling-wave parametric amplifier (TWPA) with improved control and performance. In a preferred embodiment, the amplifier comprises an integrated array of symmetric rf-SQUIDs in a transmission line structure. A device was fabricated using niobium superconducting integrated circuits, and confirmed predicted performance, with a maximum gain up to 17 dB and a bandwidth of 4 GHz. A similar device can be applied as a low-noise, low-dissipation microwave amplifier for output from a superconducting quantum computer, or as a preamplifier, switch, or frequency converter for a sensitive microwave receiver, or as an output amplifier for a frequency-multiplexed superconducting detector array.

In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.

Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

To provide a system and method for fabricating integrated circuits for superconducting applications.SOLUTION: A method of depositing a protective cap over a trilayer Josephson junction includes depositing a trilayer comprising a Nb / AlOx / Nb trilayer over a wafer, over a surface of a dielectric layer, or over a surface of a metal layer, patterning the trilayer by a lithographic process, pre-cleaning an exposed surface (e.g., a top surface) of the patterned trilayer, and depositing a protective cap over the trilayer. The cap comprises silicon nitride and serves to protect the tri-layer (specifically, the aluminum oxide layer) from degradation in subsequent processing.SELECTED DRAWING: Figure 6

This solves the connectivity problem between qubits. [Solution] The superconducting integrated circuit includes a first superconducting device 102 having a first superconducting loop 108 with a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device 104 having a second superconducting loop 112 with a second superconducting trace in a second layer. The first superconducting loop intersects with the second superconducting loop in an intersection region 120. At least a portion of each of the first and second superconducting traces inside the intersection region follows a detour path that is narrower than at least a portion of each of the traces outside the intersection region and inductively approaches at least a portion of the other path.

The present disclosure relates to superconducting integrated circuits and methods of manufacturing the same. A method of manufacturing a superconducting integrated circuit includes forming a first superconducting layer; forming a layer stack on the first superconducting layer, the layer stack comprising a Josephson junction (JJ) layer stack, a metal layer arranged on the JJ layer stack, and a fourth superconducting layer arranged on the metal layer, the JJ layer stack comprising a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer arranged on the second superconducting layer, and an electrically insulating barrier layer arranged between the second superconducting layer and the third superconducting layer; structuring the fourth superconducting layer, including performing a first etching process, the metal layer serving as an etch stop layer and a first portion of the metal layer being exposed; structuring the layer stack to form a JJ structure; forming a dielectric layer on the JJ structure; structuring the dielectric layer, including performing a second etching process, the metal layer serving as an etch stop layer and a second portion of the metal layer being exposed; forming a fifth superconducting layer on the structured dielectric layer, the fifth superconducting layer being electrically coupled to the third superconducting layer.

Systems and methods of the disclosed technology relate to hybrid integrated superconducting systems, superconducting components such as quantum wave shutters, quantum multiplexers, quantum wave memories and / or other disclosed aspects. In one example embodiment, a superconductor Metal-Oxide-Semiconductor (SMOS) chip is disclosed containing one or more superconducting components on a single die, wherein the one or more superconducting components may include a classical computing system or devices, a quantum computing system and / or devices that manipulate and control quantum waves, and a signal conversion subsystem that transforms signals between classical subsystems and quantum subsystems in order to establish a connection between classical and quantum information. Additional aspects relate to quantum devices and their structure(s) such as quantum wave shutters, quantum multiplexers and / or quantum wave memories, among other innovative systems, devices, features and functionality disclosed herein.

The application provides a superconducting integrated circuit with double-layer Josephson junctions and a preparation method thereof. The superconducting integrated circuit comprises a substrate, a logic layer and a signal transmission layer. The logic layer is located above the substrate and comprises at least one lower Josephson junction for storage and / or operation. The signal transmission layer is located above the logic layer and is electrically connected with the logic layer to transmit input and output signals of the logic layer. The signal transmission layer comprises at least one upper Josephson junction for a Josephson transmission line. The application adopts the double-layer Josephson junctions. The upper Josephson junctions can be configured without bias resistors and parallel resistors. The application is beneficial to improving the integration of the superconducting integrated circuit and the frequency of the superconducting integrated circuit. Smaller integration area of the Josephson transmission line makes the wiring of the upper signal transmission layer to the lower logic more flexible and free. In addition, the signal transmission layer can be used to manufacture passive transmission lines, further improving the integration of the superconducting integrated circuit.

A method for fabricating a superconducting integrated circuit comprises: forming a first superconducting layer; forming a layer stack above the first superconducting layer, wherein the layer stack comprises: a Josephson contact (JJ) layer stack, wherein the JJ layer stack comprises: a second superconducting layer electrically coupled to the first superconducting layer, a third superconducting layer arranged above the second superconducting layer, and an electrically insulating barrier layer arranged between the second superconducting layer and the third superconducting layer, a metal layer arranged above the JJ layer stack, and a fourth superconducting layer arranged above the metal layer;Structuring the fourth superconducting layer, comprising performing a first etching process, wherein the metal layer serves as an etch stop layer and a first section of the metal layer is exposed; structuring the layer stack to form a JJ structure; forming a dielectric layer over the JJ structure; structuring the dielectric layer, comprising performing a second etching process, wherein the metal layer serves as an etch stop layer and a second section of the metal layer is exposed; and forming a fifth superconducting layer over the structured dielectric layer, wherein the fifth superconducting layer is electrically coupled to the third superconducting layer.

To provide a superconducting device capable of more accurately arranging a non-contact coupling circuit of a superconducting integrated circuit chip and a non-contact coupling circuit of a circuit board. The chip has a first electrode made of a first superconducting material and a first non-contact coupling circuit on a surface thereof. The board has a second electrode made of a second superconducting material and a second non-contact coupling circuit on a surface thereof, and is arranged to face the chip. The second electrode has a protrusion protruding toward the chip. The protrusion includes a flat upper surface. The first electrode has a flat surface and a first recess. The first recess is arranged to face the upper surface to be located inside the upper surface of the protrusion. A third superconducting material connecting the upper surface and the first recess.

The application discloses a superconducting ring spacer and a preparation method thereof, which greatly simplifies a superconducting quantum test system, is beneficial to the large-scale development of a superconducting quantum computing circuit, and realizes compatibility with a superconducting integrated circuit in a preparation process, so that the superconducting quantum test system is greatly simplified, and the large-scale development of the superconducting quantum computing circuit is facilitated.

Systems and methods of the disclosed technology relate to hybrid integrated superconducting systems, superconducting components such as quantum wave shutters, quantum multiplexers, quantum wave memories and / or other disclosed aspects. In one example embodiment, a superconductor Metal-Oxide-Semiconductor (SMOS) chip is disclosed containing one or more superconducting components on a single die, wherein the one or more superconducting components may include a classical computing system or devices, a quantum computing system and / or devices that manipulate and control quantum waves, and a signal conversion subsystem that transforms signals between classical subsystems and quantum subsystems in order to establish a connection between classical and quantum information. Additional aspects relate to quantum devices and their structure(s) such as quantum wave shutters, quantum multiplexers and / or quantum wave memories, among other innovative systems, devices, features and functionality disclosed herein.

Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

A superconducting integrated circuit is fabricated by depositing a ground plane to at least partially overlie a substrate, depositing an insulating layer to at least partially overlie the ground plane, depositing a superconducting layer to at least partially overlie the insulating layer, and forming a superconducting feature in the superconducting layer. An inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane. The ground plane is electrically communicatively coupleable to an electrical ground. Depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material. A second critical current density of the second superconducting material is higher than a first critical current density of the first superconducting material.

A system and method for eliminating flux trapping in superconducting integrated circuits. An array of control current lines is provided, closely coupled thermally and magnetically with a superconducting integrated circuit. These control lines are configured to produce both heat and magnetic fields, with amplitudes and sequences of control currents designed to sweep magnetic flux away from the superconducting circuits at cryogenic operating temperatures. Verification may be obtained using SQUID magnetic sensors located close to the circuits. Similar methods may be applied to all superconducting integrated circuits which are sensitive to weak magnetic fields, including classical single-flux-quantum circuits, sensor arrays, and quantum computing circuits comprised of superconducting qubits. This system is scalable to superconducting circuits with up to millions of superconducting devices. The control currents may be configured to operate under automated feedback control.

Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb2O5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.

The application discloses a superconducting quantum control multiplexing device and a preparation method thereof. Embodiments of the application greatly simplify a superconducting quantum test system, are beneficial to the large-scale development of a superconducting quantum computing circuit, and realize compatibility with a superconducting integrated circuit in a preparation process.

Reset the superconducting flux storage device and the digital-to-analog converter (DAC) in a superconducting integrated circuit. [Solution] A system including a superconducting integrated circuit and a controller operates to reset each of the multiple flux storage devices by applying one or more pulses to each of the multiple flux storage devices of the superconducting integrated circuit via one of the multiple addressing lines for each power level in a sequence of discrete power levels on one of the multiple power lines.

A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.

A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.