Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Double-masking technique for increasing fabrication yield in superconducting electronics

a superconducting electronic and double-masking technology, applied in the direction of superconductor details, superconductor devices, dissimilar materials junction devices, etc., can solve the problems of major fabrication defects, improve ic yield, improve reliability and ic yield, the effect of increasing the number of steps

Inactive Publication Date: 2009-12-24
HYPRES
View PDF8 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach significantly increases the yield and quality of superconducting ICs by preventing defects during anodization and improving junction uniformity, enabling the reliable manufacturing of high-density, high-speed superconducting circuits.

Problems solved by technology

During this step, penetration of the anodization solution (the electrolyte) under the resist would cause major fabrication defects.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Double-masking technique for increasing fabrication yield in superconducting electronics
  • Double-masking technique for increasing fabrication yield in superconducting electronics
  • Double-masking technique for increasing fabrication yield in superconducting electronics

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033]A new fabrication method is proposed for increasing the yield and quality of superconducting junctions and more particularly Josephson junctions and Josephson-based digital and analog circuits in superconducting electronics. The method is based on using a double-layer mask for partial anodization of the junction side-walls and base-electrode around the junction. The top layer of this mask is a photoresist or electron-beam resist, and the bottom layer is a dielectric (e.g., SiO2) that is insoluble in either aqueous or organic solvents. A more detailed description will now be given.

[0034]The existing fabrication scheme for making Nb-based Josephson tunnel junctions for superconducting electronics is comprised of the following fabrication steps:

[0035]1. As shown in FIG. 1, a Nb / Al / AlOx / Nb trilayer is deposited in-situ on a wafer that includes or will include several other patterned layers of metal and dielectric. A tunnel barrier is formed by in-situ thermal oxidation of the Al l...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a Continuation / Division of Ser. No. 11 / 616,382, filed Dec. 27, 2006, which is expressly incorporated herein by reference. This application is related to and claims priority to Provisional Application 60 / 826,262 filed Sep. 20, 2006 by inventor Sergey K. Tolpygo entitled A Double-Masking Technique for Increasing Fabrication Yield and Josephson Junction Quality in Superconducting Electronics, the contents of which are incorporated herein by reference in its entirety.STATEMENT OF GOVERNMENT RIGHTS[0002]This invention was developed in part under contract number N0014-03-C-0370 from the Office of Naval Research.BACKGROUND OF THE INVENTION[0003]1. Field of the Invention[0004]The invention is directed to fabrication of electronic devices and more particularly to the fabrication of superconducting electronic devices such as Josephson junctions.[0005]2. Description of the Prior Art[0006]Superconducting integrated circuits (ICs) ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L39/22H01L21/302H10N60/80H10N60/01H10N60/85H10N69/00
CPCH01L39/025H01L39/2493H10N69/00H10N60/12H10N60/0912H10N60/85H10N60/0156H10N60/805H10N60/0884
Inventor TOLPYGO, SERGEY K.
Owner HYPRES
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products