Double-masking technique for increasing fabrication yield in superconducting electronics

a superconducting electronic and double-masking technology, applied in the direction of superconductor details, superconductor devices, dissimilar materials junction devices, etc., can solve the problems of major fabrication defects, improve ic yield, improve reliability and ic yield, the effect of increasing the number of steps
US20090315021A1Inactive Publication Date: 2009-12-24HYPRES
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
HYPRES
Publication Date
2009-12-24
Estimated Expiration
Not applicable · inactive patent

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Abstract

An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
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Description

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a Continuation / Division of Ser. No. 11 / 616,382, filed Dec. 27, 2006, which is expressly incorporated herein by reference. This application is related to and claims priority to Provisional Application 60 / 826,262 filed Sep. 20, 2006 by inventor Sergey K. Tolpygo entitled A Double-Masking Technique for Increasing Fabrication Yield and Josephson Junction Quality in Superconducting Electronics, the contents of which are incorporated herein by reference in its entirety.STATEMENT OF GOVERNMENT RIGHTS

[0002] This invention was developed in part under contract number N0014-03-C-0370 from the Office of Naval Research.BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The invention is directed to fabrication of electronic devices and more particularly to the fabrication of superconducting electronic devices such as Josephson junctions.

[0005] 2. Description of the Prior Art

[0006] Superconducting integrated circuits (ICs) ...

Claims

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