116 results about "Superconducting circuits" patented technology

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium / aluminum oxide / niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and / or additive patterning. A superconducting metal layer may be deposited by electroplating and / or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

Systems, methods, and apparatus for multiplexed control and readout of quantum computing systems that can include qubits, couplers, and other related quantum computing circuit devices. Numerous examples of superconducting quantum computing systems are described that include some, or all, of these quantum computing circuit devices integrated into a superconducting quantum circuit that can be interfaced by a classical control system. In one example, a superconducting circuit is described. The superconducting circuit includes: a superconducting device including a superconducting loop interrupted by one or more Josephson junctions; a first microwave resonator inductively coupled to the superconducting loop of the superconducting device; a second microwave resonator capacitively coupled to the superconducting device, where the first and second microwave resonators each have a different fundamental frequency; and a microwave transmission line evanescently coupled to each of the first and second microwave resonators.

In a general aspect, modular quantum processor configurations and methods, including integrating superconducting circuit quantum processor chips with a module integration plate that includes inter-module connections to form modular quantum processors are presented. In some cases, a quantum processing unit includes quantum processor chips, a module integration plate, and one or more caps. Each quantum processor chip includes a plurality of qubit devices. The quantum processor chips are disposed between the module integration plate and the one or more caps. The module integration plate includes recesses that house respective subsets of the quantum processor chips; and inter-module coupler devices that provide communication between the subsets of quantum processor chips housed in distinct recesses. The one or more cap wafers each includes signal lines that provide communication between at least one of the quantum processor chips and a control system.

In a general aspect, a quantum state transferring process is performed in a computing network. In some implementations, a method of transferring a quantum state between nodes in a computing network includes receiving a signal at a first node transmitted on a transmission line from a second node. The first node includes a superconducting quantum processing circuit including a tunable-frequency coupler device with a superconducting circuit loop and a first resonator device having a tunable linewidth. The first resonator device is capacitively coupled to the tunable-frequency coupler coupled to the transmission line. The second node includes a second resonator device having a fixed linewidth coupled to the transmission line. The method includes modifying the tunable linewidth of the first resonator device over time while the signal transfers a quantum state to the first resonator device from the second resonator device, by varying a magnetic flux pulse applied to the superconducting circuit loop.

The preparation method comprises the following steps: preparing a bottom-layer superconducting thin film on the surface of a substrate, preparing a bottom-layer superconducting circuit structure on the bottom-layer superconducting thin film, growing a bottom-layer aluminum thin film in a Josephson junction region, and taking the bottom-layer aluminum thin film as a lower polar plate of the Josephson junction; preparing an upper-layer superconducting circuit structure on the bottom-layer superconducting circuit structure; feeding into an oxidation chamber, and oxidizing in a controlled oxidation environment to obtain a corresponding oxide layer on the surface of the bottom aluminum film; after oxidation treatment, an upper-layer aluminum film is evaporated on the upper-layer superconducting circuit structure and stripped to a preset size, the upper-layer superconducting circuit structure serves as an upper polar plate of a Josephson junction, the area of an intersection area of the upper polar plate and a lower polar plate is 35-45 square micrometers, and the high-performance broadband Josephson parametric amplifier without an independent capacitor is achieved; the performance of the Josephson parametric amplifier is improved; meanwhile, the process complexity and the requirement for preparation equipment are reduced, the preparation efficiency is high, and the preparation cost is greatly reduced.

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

A system and method for eliminating flux trapping in superconducting integrated circuits. An array of control current lines is provided, closely coupled thermally and magnetically with a superconducting integrated circuit. These control lines are configured to produce both heat and magnetic fields, with amplitudes and sequences of control currents designed to sweep magnetic flux away from the superconducting circuits at cryogenic operating temperatures. Verification may be obtained using SQUID magnetic sensors located close to the circuits. Similar methods may be applied to all superconducting integrated circuits which are sensitive to weak magnetic fields, including classical single-flux-quantum circuits, sensor arrays, and quantum computing circuits comprised of superconducting qubits. This system is scalable to superconducting circuits with up to millions of superconducting devices. The control currents may be configured to operate under automated feedback control.

Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and / or an unexpected resistance in a superconducting resonator.

This Josephson element has: a first superconducting metal layer comprising a first surface; a second superconducting metal layer comprising a second surface facing the first surface; and an insulating layer provided between the first surface and the second surface, wherein in a plan view seen from a direction orthogonal to the first surface, the contour of the second surface is inside the contour of the first surface.

A superconducting system including a superconducting device is provided. The superconducting device includes a plurality of superconducting layers and a plurality of dielectric layers alternately arranged with the plurality of superconducting layers, and at least one of the superconducting layers is a ground plane. The superconducting device further includes a superconducting circuit present in one or more of the plurality of superconducting layers and one or more active ports extending through the plurality of superconducting layers and the plurality of dielectric layers. By activating and deactivating the one or more active ports, at least one magnetic flux vortex generated by cryogenic cooling is removed from at least one of the plurality of superconducting layers into the one or more active ports.

Systems and methods for transducing and storing qubit signals are provided. The system includes a voltage source, a substrate, and a membrane suspended over the substrate. A phononic crystal oscillator is disposed in a first region of the membrane. The phononic crystal oscillator includes a capacitor having a moving electrode including an array of multiple phononic crystal unit cells. The moving electrode is connected to the voltage source. A superconducting circuit disposed in a second region of the membrane. A plurality of phonon shields and an optical resonator may also be disposed on the membrane.

The application discloses a superconducting circuit preparation method and a quantum chip. The preparation method comprises the following steps: providing a vacuum cavity to accommodate a substrate used for preparing a superconducting circuit; forming an adsorption structure in the interior of the vacuum cavity to adsorb gas impurities in the vacuum cavity; forming a superconducting metal layer on the surface of the substrate; oxidizing the superconducting metal layer to form an oxide film on the surface of the superconducting metal layer; and patterning the superconducting metal layer to obtain the superconducting circuit. The superconducting circuit preparation method provided by the application forms an adsorption structure in the interior of the vacuum cavity before forming the superconducting metal layer on the surface of the substrate, adsorbs residual oxygen, water vapor and other gas impurities in the vacuum cavity by using the adsorption structure, further reduces the content of the gas impurities in the vacuum cavity, greatly reduces the impurity content of the superconducting metal layer formed on the substrate, and effectively guarantees that the prepared superconducting circuit has good electrical performance.

A superconducting circuit element includes a piezoelectric or ferroelectric thin film formed on a rigid substrate. The piezoelectric or ferroelectric thin film has one or more circuit element openings and an under compression room temperature superconductor material disposed within the one or more circuit element openings. Actuation of the thin film applies a compressive stress on the under compression room temperature superconductor material such that a room temperature superconducting circuit element is formed on the rigid substrate.

The invention belongs to the technical field of superconducting circuits, and particularly relates to a method and a device for determining current of a signal link coupled to a quantum bit. A shunting device is arranged on the signal link; the method comprises the following steps: acquiring electrical property influence parameters and target electrical property parameters of the shunting device, wherein the electrical property influence parameters comprise unknown sub-parameters of electrical property influence and known structure parameters obtained by measuring the product morphology of the shunting device; constructing a spice model corresponding to the shunting device by using the electrical performance influence parameters, and optimizing the sub-parameters based on the target electrical performance parameters to obtain a spice model with the target electrical performance parameters; and running a signal link comprising the spice model to obtain a current of the signal link coupled to the quantum bit. The method has the advantage that the current value coupled to the bit can be more accurately determined.

The present invention discloses a DC customized power system of superconducting circuit breaker-energy storage-fuel cell combined compensation, including a superconducting DC circuit breaker submodule and a superconducting energy storage-fuel cell combined compensation submodule; the superconducting DC circuit breaker submodule can perform zero current shutdown on the short-circuit faults on the power supply side and the load side to achieve electrical isolation; the superconducting energy storage magnet in the superconducting energy storage-fuel cell combined compensation submodule performs transient power compensation on the load side through a low-temperature power electronic superconducting converter, and the fuel cell performs steady-state uninterrupted power supply to the load side through a low-temperature power electronic battery converter. By using the superconducting circuit breaker protection, superconducting energy storage compensation and fuel cell compensation of the present invention in combination, an economical, fast and large-capacity DC customized power system can be formed.

Autonomous stabilization of a GKP code by parametric comb modulation of microwave frequencies A microwave-range quantum superconducting circuit includes an energy-tunable Josephson junction element (8) connected to a portion of a linear passive circuit (6) exhibiting several resonant modes, the first-form Foster decomposition of which across the Josephson junction element (8) includes a target resonant mode having an impedance Z greater than 13 kOhms and a pulsation w.The energy of said Josephson junction element (8) is adjustable and modulated by at least two respective pulse trains in which the pulses are separated by a duration of 2π / w and have a width less than one-tenth of this duration, the amplitude of the pulses within each respective pulse train being modulated by a respective sinusoidal carrier and the pulse trains are shifted in pairs respectively by a duration Δt such that |sin(w*Δt)| is 13 kOhms / Z, so that the resonant mode of pulsation w stabilizes in one of two GKP states encoding a qubit. Fig.2.

A superconducting circuit and a quantum computer capable of implementing four-body interaction using a plurality of superconducting qubit circuits supplied with signals of the same frequency are provided. A superconducting circuit (1) includes four superconducting qubit circuits (10), a coupling circuit (20) directly connected to the four superconducting qubit circuits (10). Each of the superconducting qubit circuits (10) indicates a qubit by being in a first phase state or a second phase state, when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an even number, an interaction term of Hamiltonian of the superconducting circuit (1) takes a first value, and when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an odd number, the interaction term takes a second value.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

The invention discloses a manufacturing method of a double-sided conduction superconducting quantum chip and a superconducting quantum computer. The manufacturing method comprises the steps of providing a substrate with a preset thickness; forming a first blind hole in the first surface in the thickness direction of the substrate; forming a first superconducting film on the inner wall of the first blind hole; forming a superconducting line on a second surface opposite to the first surface; an opening for exposing the substrate is formed in the superconducting circuit, a second blind hole communicated with the first blind hole is formed in the substrate through the opening, the depth-to-width ratio of the first blind hole to the depth-to-width ratio of the second blind hole does not exceed 2: 1, and the aperture of the second blind hole is smaller than that of the first blind hole; and forming a second superconducting film connected with the first superconducting film on the inner walls of the opening and the second blind hole. According to the invention, the depth-to-width ratio of the through hole can be reduced on the premise of not influencing the preparation and the structure of the superconducting circuit, so that the deposition difficulty of the through hole is reduced.

According to an aspect of the present inventive concept there is provided a multistage feed network for distributing a signal stage by stage for feeding a superconducting circuit. The multiple stages of the multistage feed network are arranged in a sequential order, and a plurality of two-port networks are configured to connect to two adjacent stages in between for impedance matching. At least one stage comprises a mesh network made of interconnected superconducting wires such that incoming signal(s) of said stage can be distributed to the outgoing signals of said stage by said mesh network with a minimal deviation of signal amplitude and of signal phase.

There is provided a system (1) for hosting a bosonic qubit, comprising a non-linear superconducting circuit (3) and a command circuit (5). The non-linear superconducting circuit (3) comprises: at least one resonant portion (9), and an asymmetrically threaded superconducting quantum interference device (ATS) (7) coupled to said at least one resonant portion (9), wherein the ATS (7) comprises a pair of Josephson junctions and an inductive element, wherein the pair of Josephson junctions and the inductor are galvanically connected in parallel such that each of the Josephson junctions respectively forms first and second superconducting loops with the inductive element, wherein the non-linear superconducting circuit has a first physical oscillatory mode for hosting the bosonic qubit, the first physical oscillatory mode having a first resonant frequency. The command circuit (5) comprises a first electromagnetic source (27) configured to thread the first superconducting loop with a first magnetic flux Φ 1 and the second superconducting loop with a second magnetic flux Φ 2 such that the ATS (7) is threaded with a differential flux (formula I) in units of the superconducting flux quantum. The command circuit (5) is further configured to modulate the differential flux (formula II) at a modulation frequency equal to the first resonant frequency ωa.

A superconducting controller for superconducting quantum bits is used for implementing a high-fidelity quantum gate through magnetic flux driving. The controller comprises an inductor which forms an inductance loop and is used for being coupled with a low-mutual-inductance quantum bit inductor; and a pulse shaping circuit for applying a current pulse having a predetermined shape to the inductor. The pulse shaping circuit includes: a superconducting circuit for outputting a single flux quantum (SFQ) pulse; and a digital counting circuit for generating the shape of the current (flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current of the inductor by one SFQ pulse at a time.

A write circuit for an MJJ-based memory circuit includes first and second current sources configured to generate first and second currents, respectively. The first current applies an easy axis magnetic field component to an MJJ in a selected memory cell during a write operation. The second current induces a third current through the MJJ in the selected memory cell, the third current being a seed current for setting a π-state current of the MJJ in a superconducting loop in the selected memory cell. The first current source is configured such that, during the write operation, the MJJ cell transitions from i) a π-state, in which current circulates in a clockwise or counterclockwise direction in the superconducting loop, to a zero-state, in which no current circulates in the superconducting loop, and back to the π-state; or ii) from the zero-state to the π-state; or iii) from the π-state to the zero-state.

A write circuit for writing state into a plurality of superconducting memory cells includes a control circuit, a plurality of write lines, each of the write lines being associated with a corresponding column of the superconducting memory cells and being configured to convey a write column current, and a first plurality of non-superconducting switch devices. Each of the non-superconducting switch devices are integrated with a corresponding one of the write lines and are configured to receive a first control signal supplied by the control circuit for enabling the write column current to flow through the corresponding one of the write lines for writing state into a selected one of the superconducting memory cells associated with the corresponding one of the write lines.

The various embodiments described herein include methods, devices, and systems for detecting photons. In one aspect, a superconducting circuit includes an optical waveguide and a plurality of superconducting photon detectors optically coupled to the optical waveguide. The superconducting circuit further includes a readout circuit thermally coupled to the plurality of superconducting photon detectors, the readout circuit comprising respective readout components for the plurality of superconducting photon detectors, each respective readout component having a corresponding reset component.

The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

One example includes a superconducting circuit system. The system includes at least one bias input configured to provide a bias current to a superconducting device via at least one superconducting device bias line coupled to the superconducting device during operation of the superconducting device. The system further includes a thermal transition filter system interconnecting the superconducting device bias line and the bias input. The thermal transition filter system provides a current path to divert noise current provided from the bias input away from the superconducting device during a temperature transition from a first temperature to a second temperature. The first temperature is greater than a highest superconducting critical temperature associated with the superconducting circuit system and the second temperature is less than a lowest superconducting critical temperature for the superconducting circuit system.

The invention relates to a magnetic coil arrangement (1) having at least one magnetic coil (MS1, MS2, MSN), in particular a stellarator coil or tokamak coil for a nuclear fusion system, wherein: the magnetic coil (MS1, MS2, MSN) comprises a superconducting conductor and one or more annular plate layers which are made of electrically conductive material and in each of which a plurality of windings of the superconducting conductor, which extends along a local longitudinal direction, are accommodated; the windings are arranged in succession in a local transverse direction; and the superconducting conductor of the magnetic coil (MS1, MS2, MSN) is part of a superconducting circuit of the magnetic coil arrangement (1), characterized in that at least one of the plate layers is part of an additional current path (17) which is connected in parallel with respect to at least one portion of the superconducting conductor and, with this, forms a discharge circuit (20), and in that a first switching element (S1) for interrupting the superconducting circuit is present in the superconducting circuit, wherein the switching element (S1) is arranged outside the discharge circuit (20). By means of the magnetic coil arrangement according to the invention, when local heating of the conductor occurs, firstly the magnetic coil can be quickly discharged and secondly the voltage prevailing across the conductor and relative to ground can be limited to an acceptable level.

A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

One example includes a superconducting circuit. The circuit includes superconducting circuitry fabricated in a circuit layer. The circuit layer includes a first surface and a second surface opposite the first surface. The circuit also includes a flux moat comprising a dielectric material formed in the circuit layer. The flux moat can be configured to trap a magnetic flux as the superconducting circuit is cooled to below a superconducting critical temperature. The circuit further includes a magnetic film arranged proximal to the flux moat on at least one of the first and second surfaces of the circuit layer. The magnetic film can be configured to guide the magnetic flux to the flux moat as the superconducting circuit is cooled to below the superconducting critical temperature.