87results about "Logic circuits using superconductive devices" patented technology

A system and method for inducing spin locking onto superconducting qubits, via a control drive, during performance of a quantum gate between the superconducting qubits is described. Spin locking may prolong the coherence times of the superconducting qubits involved in the gate, therefore reducing the risk that a fault occurs due to interference by noise in the environment. In order to induce spin locking, pulses may be directed at the superconducting qubits for the duration of the gate. The pulses may be determined and optimized by optimal coherence control methods and applied using a control drive. The pulse profiles may be determined in a manner that is specific to the given gate, to the superconducting qubits involved in the gate, and to the quantum hardware upon which the superconducting qubits and the gate are implemented.

Techniques are described for operating a qubit controller to generate a signal to apply to a qubit using a tunable coupler that controls the amplitude of at least part of the signal. The qubit controller may comprise a plurality of digital-to-analog converters that each convert digital values to an analog waveform. The qubit controller may further comprise a plurality of tunable couplers each coupled to a respective DAC that adjusts the amplitude of the analog waveform from the respective DAC. The tunable couplers thereby produce a plurality of analog waveforms, which may be combined to produce a signal to apply to the qubit. In some embodiments, the tunable couplers may each be configured to receive a respective control signal that dictates the scaling factor which that tunable coupler applies to the analog waveform.

One example includes a superconducting data input system. The system includes an inductive coupler that generates first and second bias currents in response to receiving a current pulse. The system also includes a first clocked receiver configured to generate a first superconducting data signal having a first data state in response to the first bias current at a first phase of a clock signal, and a second data state in response to not receiving the first bias current at the first phase of the clock signal. The system further includes a second clocked receiver configured to generate a second superconducting data signal having the first data state in response to the second bias current at a second phase of the clock signal different from the first phase, and having the second data state in response to not receiving the second bias current at the second phase of the clock signal.

Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (400) for interfacing with qubit gates comprises a first plurality of devices (420) configured to operate in a cryogenic environment; a second plurality of devices (430), different from the first plurality of devices (420), configured to operate in the cryogenic environment; and control logic (450). The control logic (450) is coupled to each of the first plurality of devices (420) and the second plurality of devices (430), and is configured to modify a threshold voltage associated with each of the first plurality of devices (420) and the second plurality of devices (430) such that a first threshold voltage associated with each of the first plurality of devices (420) is different from a second threshold voltage associated with each of the second plurality of devices (430).

Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

A flux switch system is disclosed. The system (50) includes an input stage (52) configured to provide an interrogation pulse. The system also includes a plurality of flux loops (62, 64) configured to receive an input current (IIN). Each of the flux loops includes a Josephson junction (J1, J2) configured to trigger to generate an output pulse in response to a first polarity of the input current and to not trigger to generate no output pulse in response to a second polarity of the input current opposite the first polarity. The system further includes an output stage (54) configured to propagate the output pulse to an output (INTout) of the flux switch system.

A superconducting circuit and a quantum computer capable of implementing four-body interaction using a plurality of superconducting qubit circuits supplied with signals of the same frequency are provided. A superconducting circuit (1) includes four superconducting qubit circuits (10), a coupling circuit (20) directly connected to the four superconducting qubit circuits (10). Each of the superconducting qubit circuits (10) indicates a qubit by being in a first phase state or a second phase state, when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an even number, an interaction term of Hamiltonian of the superconducting circuit (1) takes a first value, and when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an odd number, the interaction term takes a second value.

A reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

A superconducting controller for superconducting quantum bits is used for implementing a high-fidelity quantum gate through magnetic flux driving. The controller comprises an inductor which forms an inductance loop and is used for being coupled with a low-mutual-inductance quantum bit inductor; and a pulse shaping circuit for applying a current pulse having a predetermined shape to the inductor. The pulse shaping circuit includes: a superconducting circuit for outputting a single flux quantum (SFQ) pulse; and a digital counting circuit for generating the shape of the current (flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current of the inductor by one SFQ pulse at a time.

A quantum information system comprising a quantum information element and a control line, the quantum information element comprising: a first Josephson element and a second Josephson element, each Josephson element comprising a Josephson junction disposed between two superconducting islands, one of the superconducting islands is shared by the first Josephson element and the second Josephson element; wherein the superconducting island of the first Josephson element is coupled to the superconducting island of the second Josephson element such that the quantum information element comprises a plurality of states, the plurality of states comprising a first state, a second state, and a third state, where there is a single excitation transition between the third state and the first state, and there is a single excitation transition between the third state and the second state; and wherein the control line is configured to encode one of two states of the computing subspace into the quantum information element, a first state of the computing subspace corresponding to the first state, and a second state of the computing subspace corresponding to the second state.

In a general aspect, quantum-assisted two-sample test is presented. In some implementations, a hybrid computer system configured to evaluate data points in a dataset includes a quantum computing system and a classical computing system. The classical computing system is configured to cause the quantum computing system to execute a quantum logic circuit to encode the data points from the dataset in the quantum logic circuit which includes at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtain measurements of expectation values of quantum states generated by executing the quantum logic circuit on the quantum computing system; determining a quantum density operator associated with the dataset, the quantum density operator being determined based on the measurements; and determining a data characteristic of the dataset based on the quantum density operator.

One example includes a superconducting data input system. The system includes an inductive coupler that generates first and second bias currents in response to receiving a current pulse. The system also includes a first clocked receiver configured to generate a first superconducting data signal having a first data state in response to the first bias current at a first phase of a clock signal, and a second data state in response to not receiving the first bias current at the first phase of the clock signal. The system further includes a second clocked receiver configured to generate a second superconducting data signal having the first data state in response to the second bias current at a second phase of the clock signal different from the first phase, and having the second data state in response to not receiving the second bias current at the second phase of the clock signal.

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

A cryogenic cooling system for use in quantum computing applications can include a plurality of cryogenic cooling stages. Each of the plurality of cryogenic cooling stages can include a plurality of interleaved cooling units. The plurality of interleaved cooling units can include a first cooling unit and a second cooling unit. Each of the plurality of interleaved cooling units can have an associated operating temperature range. One or more signal lines that couple one or more classical processors to one or more quantum systems can pass through each of the plurality of interleaved cooling units for each of the plurality of cryogenic cooling stages.

A quantum node includes one or more communication qubits, one or more interior qubits coupled to the one or more communication qubits with interior tunable couplers, a communication tunable coupler coupled to each of the one or more communication qubits, and a communication resonator coupled to each of the communication tunable couplers. In addition, a distributed quantum computing system includes two or more quantum nodes, and one or more coaxial cables or coplanar waveguides connecting the two or more quantum nodes together using at least one of the communication resonators of the two or more quantum nodes. Entanglement and fabrication methods of the quantum nodes are also described.

In a general aspect, quantum-assisted two-sample test is presented. In some implementations, a hybrid computer system configured to evaluate data points in a dataset includes a quantum computing system and a classical computing system. The classical computing system is configured to cause the quantum computing system to execute a quantum logic circuit to encode the data points from the dataset in the quantum logic circuit which includes at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtain measurements of expectation values of quantum states generated by executing the quantum logic circuit on the quantum computing system; determining a quantum density operator associated with the dataset, the quantum density operator being determined based on the measurements; and determining a data characteristic of the dataset based on the quantum density operator.

A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

One example includes a PTL receiver system. The system includes a receiver core that comprises an input Josephson junction and that receives an input pulse from a PTL. The system also includes an active bias circuit which generates a bias pulse based on a bias clock signal and provides the bias pulse to the receiver core. The bias pulse can have a pulse-width approximately one-half a period of the bias clock signal. The input Josephson junction can trigger to generate an intermediate pulse in response to the input and bias pulses. The system further includes an alignment JTL comprising at least one alignment Josephson junction. The alignment Josephson junction can be configured to trigger to generate an output pulse in response to the intermediate pulse and the bias clock signal to provide for reception of the input pulse across a wide timing window based on the bias pulse.

A reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

A device comprising a plurality of independent rotating gates, each rotating gate comprising a magnet configured to generate a magnetic field of a predetermined strength at a qubit location of the respective rotating gate. The magnetic field is configured to generate a qubit resonant frequency at the qubit location due to a magnetically sensitive electronic state of the qubit. The device further comprises a first electromagnetic field source configured to generate an electromagnetic field at the resonant frequency for a predetermined period across the plurality of independent rotating gates. Each independent rotating gate comprises a controller configured to independently take the qubit off resonance at each independent rotating gate at a predetermined time within the predetermined period.

This invention provides a device and method for achieving site-specific gate control for magnetically sensitive qubits in quantum computing. [Solution] A device comprising a plurality of independent rotary gates, each rotary gate comprising a magnet that generates a magnetic field structure 10, 11 of a predetermined strength at the qubit position of the respective rotary gate, the magnetic field generating the resonance frequency of the qubit at the qubit position due to the magnetically sensitive electronic state of the qubit 15. The device also comprises a first electromagnetic field source 26-29 that generates an electromagnetic field of the resonance frequency over a predetermined period of time across the plurality of independent rotary gates. Each independent rotary gate comprises a controller 41 that independently de-resonates the qubit at a predetermined time within the predetermined period.

A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

The inventors have developed techniques to facilitate the operation of a quantum oscillator with increased bit-flip lifetimes by inducing an energetic asymmetry between qubit states. The technology may be used for the storage of quantum information or for providing a system for quantum information processing with longer bit flip lifetimes. The technology includes a qubit along with corresponding drives for controlling the energetic barrier and energetic asymmetry between the energetic potentials for each qubit state.

Output amplifier comprising a stack of compound superconducting quantum interference device (SQUID) output amplifier stages and related methods are provided. A method includes receiving a first pulse train comprising a first plurality of single flux quantum (SFQ) pulses. The method may further include receiving a second pulse train comprising a second plurality of SFQ pulses, where the second pulse train is delayed by a predetermined fraction of a clock cycle relative to the first pulse train. The method may further include using the stack of the plurality of compound SQUID output amplifier stages converting the first plurality of SFQ pulses and the second plurality of SFQ pulses into a voltage waveform, where each of the plurality of compound SQUID output amplifier stages comprises a pair of superconducting quantum interference devices (SQUIDs).

This qubit control circuit includes a first power supply line through which a first excitation current is input, a second power supply line through which a second excitation current is input, a first input signal line through which a first input signal is input, a first pulse train generation circuit that outputs a first pulse train having a repetition frequency corresponding to a frequency of the first excitation current generated by a first Josephson junction on the basis of a frequency of the first excitation current, a waveform of the second excitation current, and a logical state indicated by the first input signal, a second pulse train generation circuit that outputs a second pulse train having a repetition frequency corresponding to the frequency of the first excitation current generated by a second Josephson junction on the basis of the frequency of the first excitation current, and an output pulse train generation circuit that includes a third Josephson junction and outputs an output pulse train in which a waveform of the first pulse train is shaped by a repetition frequency of the second pulse train.

A resonator, an oscillator, and a quantum computer in which both moderate nonlinearity and a low loss are achieved, and the area occupied by the circuit can be reduced are provided. A resonator (100) includes at least one loop circuit (110) in which a first superconducting line (101), a first Josephson junction (103), a second superconducting line (102), and a second Josephson junction (104) are connected in a ring shape, at least one third Josephson junction (130) provided separately from the Josephson junction included in the loop circuit (110), and a capacitor (120), in which the loop circuit (110), the third Josephson junction (130), and the capacitor (120) are connected in a ring shape.