29results about "Logic circuits using superconductive devices" patented technology

Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

A flux switch system is disclosed. The system (50) includes an input stage (52) configured to provide an interrogation pulse. The system also includes a plurality of flux loops (62, 64) configured to receive an input current (IIN). Each of the flux loops includes a Josephson junction (J1, J2) configured to trigger to generate an output pulse in response to a first polarity of the input current and to not trigger to generate no output pulse in response to a second polarity of the input current opposite the first polarity. The system further includes an output stage (54) configured to propagate the output pulse to an output (INTout) of the flux switch system.

A cryogenic cooling system for use in quantum computing applications can include a plurality of cryogenic cooling stages. Each of the plurality of cryogenic cooling stages can include a plurality of interleaved cooling units. The plurality of interleaved cooling units can include a first cooling unit and a second cooling unit. Each of the plurality of interleaved cooling units can have an associated operating temperature range. One or more signal lines that couple one or more classical processors to one or more quantum systems can pass through each of the plurality of interleaved cooling units for each of the plurality of cryogenic cooling stages.

A quantum node includes one or more communication qubits, one or more interior qubits coupled to the one or more communication qubits with interior tunable couplers, a communication tunable coupler coupled to each of the one or more communication qubits, and a communication resonator coupled to each of the communication tunable couplers. In addition, a distributed quantum computing system includes two or more quantum nodes, and one or more coaxial cables or coplanar waveguides connecting the two or more quantum nodes together using at least one of the communication resonators of the two or more quantum nodes. Entanglement and fabrication methods of the quantum nodes are also described.

A reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

This invention provides a device and method for achieving site-specific gate control for magnetically sensitive qubits in quantum computing. [Solution] A device comprising a plurality of independent rotary gates, each rotary gate comprising a magnet that generates a magnetic field structure 10, 11 of a predetermined strength at the qubit position of the respective rotary gate, the magnetic field generating the resonance frequency of the qubit at the qubit position due to the magnetically sensitive electronic state of the qubit 15. The device also comprises a first electromagnetic field source 26-29 that generates an electromagnetic field of the resonance frequency over a predetermined period of time across the plurality of independent rotary gates. Each independent rotary gate comprises a controller 41 that independently de-resonates the qubit at a predetermined time within the predetermined period.

The inventors have developed techniques to facilitate the operation of a quantum oscillator with increased bit-flip lifetimes by inducing an energetic asymmetry between qubit states. The technology may be used for the storage of quantum information or for providing a system for quantum information processing with longer bit flip lifetimes. The technology includes a qubit along with corresponding drives for controlling the energetic barrier and energetic asymmetry between the energetic potentials for each qubit state.

Output amplifier comprising a stack of compound superconducting quantum interference device (SQUID) output amplifier stages and related methods are provided. A method includes receiving a first pulse train comprising a first plurality of single flux quantum (SFQ) pulses. The method may further include receiving a second pulse train comprising a second plurality of SFQ pulses, where the second pulse train is delayed by a predetermined fraction of a clock cycle relative to the first pulse train. The method may further include using the stack of the plurality of compound SQUID output amplifier stages converting the first plurality of SFQ pulses and the second plurality of SFQ pulses into a voltage waveform, where each of the plurality of compound SQUID output amplifier stages comprises a pair of superconducting quantum interference devices (SQUIDs).

A resonator, an oscillator, and a quantum computer in which both moderate nonlinearity and a low loss are achieved, and the area occupied by the circuit can be reduced are provided. A resonator (100) includes at least one loop circuit (110) in which a first superconducting line (101), a first Josephson junction (103), a second superconducting line (102), and a second Josephson junction (104) are connected in a ring shape, at least one third Josephson junction (130) provided separately from the Josephson junction included in the loop circuit (110), and a capacitor (120), in which the loop circuit (110), the third Josephson junction (130), and the capacitor (120) are connected in a ring shape.

A system and method are provided for determining critical timing paths in a superconducting circuit design including a Josephson junction. An example method includes providing timing information about a plurality of source terminals of at least one logic gate coupled to a first terminal of the at least one logic gate. The method further includes using a processor to determine, based on a first phase assigned to the at least one logic gate and in view of the timing information, whether the first terminal is reachable by a single-throughput quantum SFQ pulse within a predetermined time range.

A superconducting controller for a superconducting qubit that executes a high-fidelity quantum gate using magnetic flux drive. The controller includes the following components: an inductance configured to form an inductive loop and inductively couple with a qubit with a small mutual inductance; and a pulse shaping circuit configured to apply a current pulse of a predetermined shape to the inductance. The pulse shaping circuit includes: a superconducting circuit that outputs a single-flux quantum (SFQ) pulse; and a digital counter circuit that generates the shape of the current (magnetic flux) pulse applied to the inductor loop by increasing or decreasing the current flowing through the inductance by 1 SFQ pulse at a time.

One example aspect of the present disclosure is directed to a method for characterizing a multi-qubit logic gate operating on a pair of qubits. The method includes iteratively performing, via a multi-qubit quantum circuit, a set of serial operations on the pair of qubits. The multi-qubit quantum circuit includes the multi-qubit logic gate, a first single-qubit logic gate operating on the first qubit, and a second single-qubit logic gate operating on the second qubit. After iteratively performing the set of serial operations on the pair of qubits, a first quantum state of the first qubit and a second quantum state of the second qubit are measured. A first set of expectation values for the first qubit and a second set of expectation values for the second qubit are determined. A value for a first parameter of a set of parameters of the multi-qubit logic gate is determined.

One example includes a long Josephson junction gate system. The system includes at least one input long Josephson junction (Josephson junction) configured to propagate a respective at least one input signal. The system also includes a long Josephson junction gate comprising at least one gate long Josephson junction configured to provide a logic operation based on the at least one input signal and to provide at least one output signal. The system further includes at least one output long Josephson junction configured to propagate the respective at least one output signal.

The technology relates to electrical devices comprising a length of superconducting material with a critical current when current travels in one direction is different to a critical current of the length of superconducting material when current travels through the length of superconducting material in an opposite direction. The electrical device may further comprise a magnetic field generator comprising two permanent magnets positioned on the same side of the length of superconducting material and arranged substantially anti-parallel to each other. The polar axes of the two permanent magnets may be oriented substantially perpendicular to the faces of the length of superconducting material.

Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

One example includes an amplifier system. The system includes an input configured to receive an input pulse, a first input path coupled to the input and configured to provide the input pulse to a control node, and a second input path coupled to the input and comprising at least one delay element to provide a delayed version of the input pulse to the control node. The system also includes a first amplifier device comprising the control node and being configured to provide a control flux in response to the input pulse and in response to the delayed version of the input pulse. The system further includes a second amplifier device coupled to the first amplifier device, the second amplifier device being set to a flux state in response to the control flux to provide an output voltage.

An example electric circuit includes a superconducting component having a first terminal, a second terminal, and a constriction region between the first terminal and the second terminal. The example circuit also includes a non-superconducting component having a third terminal and a fourth terminal. The non-superconducting component has a first portion that is connected to the third terminal, a second portion that is connected to the fourth terminal, and a third portion that is between the first portion and second portion. The third portion is positioned closer to the constriction region than the first portion and second portion such that heat produced at the non-superconducting component transfers to the superconducting component without dissipating from the superconducting component back to the non-superconducting component.

A programmable circuit includes a superconducting multi-dimensional array. The programmable circuit further includes a plurality of photon detectors coupled to respective portions of the superconducting multi-dimensional array, each photon detector configured to selectively provide input to a corresponding respective portion sufficient to transition the corresponding respective portion from a superconducting state to a non-superconducting state. The programmable circuit also includes one or more electrical terminals coupled to respective second portions of the superconducting multi-dimensional array.

Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a "body" circuit that provides a single or multi-state sub-critical bias current to one or many independent "tail" circuitries. Each "tail" has minimal effect on the "body" thereby preventing any interference or destruction to the state of the "body" circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

A capacitively-driven tunable coupler includes a coupling capacitor connecting an open end of a quantum object (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without breaking the functionality of the object) to an RF SQUID having a Josephson element capable of providing variable inductance and therefore variable coupling to another quantum object.

To provide a superconducting quantum circuit including four-body interaction coupler that has an excellent noise resistance characteristic and is applicable to an actual application.SOLUTION: A four-body interaction coupler, in a planer circuit configuration, comprises a first electrode and a second electrode disposed facing each other and away from a circumambient ground pattern, the first electrode being provided with a first facing part and a second facing part that extend from a portion of the first electrode different from the side facing the second electrode toward sides of a first quantum bit and a second quantum bit, respectively, the second electrode being provided with a first facing part and a second facing part that extend from a portion of the second electrode different from the side facing the first electrode toward sides of third quantum bit and forth quantum bit, respectively, and provided with a non-liner device including a Josephson junction crosslinking the first electrode and the second electrode, at least one of a gap width between the first electrode and the ground pattern facing the first electrode and a gap width between the second electrode and the ground pattern facing the second electrode is set to a value equal to or a fraction of a size of the first electrode or the second electrode.SELECTED DRAWING: Figure 3

The invention provides a method for operating at least one CMOS transistor at a low temperature, the at least one CMOS transistor produced using at least one process selected from a planar bulk CMOS process, a fin field effect transistor (FinFET) process, and a combination thereof, the method comprising setting the at least one CMOS transistor in a low-temperature drive mode comprising determining for the at least one CMOS transistor its threshold voltage as a function of its operating temperature range and for an applied forward bulk biasing voltage, selecting a desired threshold voltage and a desired operating temperature in the operating temperature range for the at least one CMOS transistor, in particular a desired operating temperature below 218K, more in particular at a cryogenic temperature, determining a resulting forward bulk biasing (FBB) voltage, and applying the resulting forward bulk biasing voltage to the at least one CMOS transistor.