153results about "Logic circuits using superconductive devices" patented technology

Methods and systems for classical processing in a quantum controller.

A system and method for inducing spin locking onto superconducting qubits, via a control drive, during performance of a quantum gate between the superconducting qubits is described. Spin locking may prolong the coherence times of the superconducting qubits involved in the gate, therefore reducing the risk that a fault occurs due to interference by noise in the environment. In order to induce spin locking, pulses may be directed at the superconducting qubits for the duration of the gate. The pulses may be determined and optimized by optimal coherence control methods and applied using a control drive. The pulse profiles may be determined in a manner that is specific to the given gate, to the superconducting qubits involved in the gate, and to the quantum hardware upon which the superconducting qubits and the gate are implemented.

Techniques are described for operating a qubit controller to generate a signal to apply to a qubit using a tunable coupler that controls the amplitude of at least part of the signal. The qubit controller may comprise a plurality of digital-to-analog converters that each convert digital values to an analog waveform. The qubit controller may further comprise a plurality of tunable couplers each coupled to a respective DAC that adjusts the amplitude of the analog waveform from the respective DAC. The tunable couplers thereby produce a plurality of analog waveforms, which may be combined to produce a signal to apply to the qubit. In some embodiments, the tunable couplers may each be configured to receive a respective control signal that dictates the scaling factor which that tunable coupler applies to the analog waveform.

One example includes a superconducting data input system. The system includes an inductive coupler that generates first and second bias currents in response to receiving a current pulse. The system also includes a first clocked receiver configured to generate a first superconducting data signal having a first data state in response to the first bias current at a first phase of a clock signal, and a second data state in response to not receiving the first bias current at the first phase of the clock signal. The system further includes a second clocked receiver configured to generate a second superconducting data signal having the first data state in response to the second bias current at a second phase of the clock signal different from the first phase, and having the second data state in response to not receiving the second bias current at the second phase of the clock signal.

Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (400) for interfacing with qubit gates comprises a first plurality of devices (420) configured to operate in a cryogenic environment; a second plurality of devices (430), different from the first plurality of devices (420), configured to operate in the cryogenic environment; and control logic (450). The control logic (450) is coupled to each of the first plurality of devices (420) and the second plurality of devices (430), and is configured to modify a threshold voltage associated with each of the first plurality of devices (420) and the second plurality of devices (430) such that a first threshold voltage associated with each of the first plurality of devices (420) is different from a second threshold voltage associated with each of the second plurality of devices (430).

Embodiments of the present disclosure provide a pixel circuitry, a drive method thereof, an array substrate and a display panel. The pixel circuitry includes circuits designated: drive CD, data write CDW, initialization CI, first light emission control CLEC1, first storage CS1, second storage CS2 and second light emission control CLEC2. CD connects to first through third nodes N1-N3 and provides drive current to a light emitting device. CDW connects to N1 and provides a data signal to CD according to a drive signal. CI provides an initialization signal to N2 according to a reset signal. CLEC1 provides a first voltage signal to N3 according to a first light emission control signal. CS1 and CS2 store a voltage difference between the first voltage signal terminal and N2, and N1 and N2, respectively. CLEC2 controls the drive current to the light emitting device according to a second light emission control signal.

Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a low temperature. The system also includes a second packaged device including a control circuit configured to operate at a low temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit includes a plurality of charge locking circuits configured to lock the charge of the first packaged device to the second packaged device. Wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system further includes a second packaging device including a control circuit configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit includes a plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

A flux switch system is disclosed. The system (50) includes an input stage (52) configured to provide an interrogation pulse. The system also includes a plurality of flux loops (62, 64) configured to receive an input current (IIN). Each of the flux loops includes a Josephson junction (J1, J2) configured to trigger to generate an output pulse in response to a first polarity of the input current and to not trigger to generate no output pulse in response to a second polarity of the input current opposite the first polarity. The system further includes an output stage (54) configured to propagate the output pulse to an output (INTout) of the flux switch system.

The present invention relates to a quantum magnetic field receiving device including a superconducting quantum interference device (SQUID) or a superconducting quantum interference filter (SQIF) and an electrostatic gating circuit configured to apply electrostatic fields to Josephson Junctions of the SQUID or SQIF.

A superconducting circuit and a quantum computer capable of implementing four-body interaction using a plurality of superconducting qubit circuits supplied with signals of the same frequency are provided. A superconducting circuit (1) includes four superconducting qubit circuits (10), a coupling circuit (20) directly connected to the four superconducting qubit circuits (10). Each of the superconducting qubit circuits (10) indicates a qubit by being in a first phase state or a second phase state, when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an even number, an interaction term of Hamiltonian of the superconducting circuit (1) takes a first value, and when the number of the superconducting qubit circuits (10) in the first phase state among the four superconducting qubit circuits (10) is an odd number, the interaction term takes a second value.

A thermodynamic relay gadget includes a relay oscillator and an on-chip controller. The relay oscillator has a time dependent mass or time dependent frequency that is controllable, by the on-chip controller. The relay gadget is configured to relay thermodynamic information in analog form between an output oscillator of a first energy-based model and an input oscillator of a second energy-based model.

Technologies for performing error correction in a quantum circuit of a quantum computing system are disclosed. A quantum error correction code (QECC) is selected. The QECC is associated with a codespace. The quantum computing system identifies, based on one or more properties of the QECC, one or more diagonal physical gates in the quantum circuit that induces a target logical gate and preserves the codespace. The quantum computing system configures the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified diagonal physical gates.

Systems and methods for determining timing paths and reconciling topology in a superconducting circuit design are provided. The design may include a first timing path having a first set of timing pins associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. An example method includes processing (step 1510) the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method further includes inserting (step 1520) a first shadow element (fig. 9: 914) representing a first physically connected component on the timing path, where the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method further includes addressing (step 1530) any changes to the first legal start time or the second legal start time caused by an insertion of the first shadow element on the timing path.

A reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

A milliohm resistor is fabricated as a Josephson junction device that contains ferromagnetic or antiferromagnetic material (206, 210, 416) of sufficient thickness to render the device entirely resistive between terminals. The device can have a resistance on the order of milliohms and can consume a much smaller chip footprint than resistors of the same resistance fabricated using conventional resistive materials. Because the device can be fabricated without modification to processes used to fabricate reciprocal quantum logic (RQL) circuitry, it can easily be incorporated in RQL circuits to mitigate flux trapping or to perform other functions where very small resistances are needed. lii particular, the device can burn off circulating currents induced by trapped flux without affecting the transmission of SFQ pulses through RQL circuitry.

A method is provided, including: applying a magnetic field according to a two-qubit gate operation performed with a quantum device; transmitting a voltage signal to a gate structure, arranged above first and second quantum dots in the quantum device, to generate a coupling signal that includes a first sine squared wave; and performing, by the magnetic field and the coupling signal, the two-qubit gate operation to the first and second qubits in the first and second quantum dots.

A superconducting controller for superconducting quantum bits is used for implementing a high-fidelity quantum gate through magnetic flux driving. The controller comprises an inductor which forms an inductance loop and is used for being coupled with a low-mutual-inductance quantum bit inductor; and a pulse shaping circuit for applying a current pulse having a predetermined shape to the inductor. The pulse shaping circuit includes: a superconducting circuit for outputting a single flux quantum (SFQ) pulse; and a digital counting circuit for generating the shape of the current (flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current of the inductor by one SFQ pulse at a time.

A method, system, and computer program product for implementing a quantum fan-out operation. A fan-out gate is constructed using ladders of CNOT gates in a constant depth using a dynamic quantum circuit. Constant depth refers to the depth or number of time steps being independent of the number of qubits. A dynamic quantum circuit is a quantum circuit with mid-circuit measurements and feed-forward classical operations which allows such circuits to be adaptive on-the-fly. The quantum fan-out operation is implemented by the fan-out gate using ancilla qubits and feed-forward operations. In this manner, the quantum fan-out operation can be implemented on superconducting devices at a reduced depth (constant depth) with fewer CNOT gates as well as using fewer ancilla qubits.

A quantum information system comprising a quantum information element and a control line, the quantum information element comprising: a first Josephson element and a second Josephson element, each Josephson element comprising a Josephson junction disposed between two superconducting islands, one of the superconducting islands is shared by the first Josephson element and the second Josephson element; wherein the superconducting island of the first Josephson element is coupled to the superconducting island of the second Josephson element such that the quantum information element comprises a plurality of states, the plurality of states comprising a first state, a second state, and a third state, where there is a single excitation transition between the third state and the first state, and there is a single excitation transition between the third state and the second state; and wherein the control line is configured to encode one of two states of the computing subspace into the quantum information element, a first state of the computing subspace corresponding to the first state, and a second state of the computing subspace corresponding to the second state.

In a general aspect, quantum-assisted two-sample test is presented. In some implementations, a hybrid computer system configured to evaluate data points in a dataset includes a quantum computing system and a classical computing system. The classical computing system is configured to cause the quantum computing system to execute a quantum logic circuit to encode the data points from the dataset in the quantum logic circuit which includes at least one layer of single-qubit quantum logic gates and at least one layer of multi-qubit quantum logic gates; obtain measurements of expectation values of quantum states generated by executing the quantum logic circuit on the quantum computing system; determining a quantum density operator associated with the dataset, the quantum density operator being determined based on the measurements; and determining a data characteristic of the dataset based on the quantum density operator.

One example includes a superconducting data input system. The system includes an inductive coupler that generates first and second bias currents in response to receiving a current pulse. The system also includes a first clocked receiver configured to generate a first superconducting data signal having a first data state in response to the first bias current at a first phase of a clock signal, and a second data state in response to not receiving the first bias current at the first phase of the clock signal. The system further includes a second clocked receiver configured to generate a second superconducting data signal having the first data state in response to the second bias current at a second phase of the clock signal different from the first phase, and having the second data state in response to not receiving the second bias current at the second phase of the clock signal.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (700) includes a plurality of devices (760) configured to operate in a cryogenic environment (<300 K), where a first distribution of a threshold voltage associated with the plurality of devices (760) has a first value indicative of a measure of spread of the threshold voltage. The system (700) further includes control logic (712, 714), coupled to each of the plurality of devices (760), configured to modify (714out) a threshold voltage associated with each of the plurality of devices (760) such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.

A method, apparatus, and system for fully randomized benchmarking of quantum circuits include: generating representations of m1 random unitary quantum gates based on parameters of quantum gates; determining a representation of a first quantum gate sequence equivalent to an identity operator; determining a representation of a second quantum gate sequence equivalent to the identity operator; sending hardware instructions corresponding to the representation of the first quantum gate sequence and hardware instructions corresponding to the representation of the second quantum gate sequence to a quantum computing device; receiving a first number of measurements of the quantum bit from the quantum computing device after the quantum computing device applies the first quantum gate sequence to the quantum bit for a first number, and receiving a second number of measurements of the quantum bit from the quantum computing device after the quantum computing device applies the second quantum gate sequence to the quantum bit for a second number; and determining a fidelity value of the quantum gate based on a first probability and a second probability.

Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.