57results about "Manipulation for frequency change" patented technology

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

According to the present disclosure there is provided a control circuit for a packaged semiconductor chip rail guide tapper driving means, comprising a control signal generator configured to generate control signals at a control frequency, and a drive module arranged to receive the control signals and output drive signals to the driving means based on the control signals to drive a rail guide tapper to tap a rail guide at a tapping frequency corresponding to the control frequency.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

Systems, apparatuses, and methods for managing power and performance in a computing system. A system management unit detects a condition indicating a change in a power-performance state of a given computing unit is indicated. In response to detecting the indication, the system management unit is configured to initiate a change to a frequency of a clock signal generated by an adaptive oscillator by changing a voltage supplied to the adaptive oscillator. The adaptive oscillator is configured to rapidly change a frequency of the clock signal generated in response to detecting a change in a droopy supply voltage of the adaptive oscillator. The new frequency generated by the adaptive oscillator is based in part on a difference between the droopy supply voltage and a regulated supply voltage of the adaptive oscillator.

The embodiment of the invention discloses a device with a clock signal generator and a method for sampling an input signal. The device comprises a first clock signal generator, a second clock signal generator, an input signal generation circuit and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a functional circuit. The voltage signal generator generates a voltage signal. The functional circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples a value of the voltage signal at a rising edge or a falling edge of the second clock signal and provides the sampled value as an output signal to analyze one or more characteristics of the voltage signal based on the output signal.

A circuit (12), comprising: frequency multiplier circuitry (120) having input nodes (INp, INN) configured to receive an input signal (Vf0) and an anti-phase version thereof, the input signal (Vf0) having a first frequency value, the frequency multiplier circuitry (120) configured to produce a current signal (i2f0) at a second frequency value that is an even multiple of the first frequency value; a transformer (122) comprising a primary side (Lp, Cp) and a secondary side (Ls, Cs), wherein the primary side (Lp, Cp) of the transformer (122) comprises a primary inductance (Lp) coupled (126) to the frequency multiplier circuitry (120) to receive the current signal (i2f0) therefrom, wherein the secondary side (Ls, Cs) of the transformer (122) is configured to provide a frequency multiplied voltage signal (VOUT); wherein the frequency multiplier circuitry (120) and the transformer (122) are cascaded between at least one first node (D) and a second node (S), the at least one first node (D) and the second node (S) configured to be coupled to a supply node (VDD) and ground (GND); a first shunt resonator (124a) coupled between the supply node (VDD) and the at least one first node (D); a second shunt resonator (124b) coupled between the second node (S) and ground (GND), and a bypass current path (126) coupled between the at least one first node (D) and the second node (S).

A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

In an embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to divide the output clock signal to generate a divided clock signal, a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to generate a gain error signal, and modify the bias control word based on the gain error signal to generate a modified bias control word.

A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.

In one embodiment, a frequency synthesizer comprises a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to produce a gain error signal.and to modify the bias control word based on the gain error signal to create a modified bias control word.

A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.

A method to generate a crystal oscillator clock having a duty cycle via a first stage of a clock circuit, double the crystal oscillator clock and inputting the doubled crystal oscillator clock into a phased-locked loop, feed back a phase-locked loop feedback clock, measure a difference in delay between a first edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock and a second edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock, and adjust the duty cycle of the crystal oscillator clock based on the difference in delay. A device having a detection circuit to measure a difference in delay between first and second edges of a doubled crystal oscillator clock output relative to a phase-locked loop feedback clock, and a controller to adjust the duty cycle of the clock output based on the difference in delay.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

A frequency multiplier includes a first ring oscillator, a second ring oscillator that is turned on complementarily to the first ring oscillator, a combining circuit that combines a first output signal of the first ring oscillator and a second output signal of the second ring oscillator to generate a final output signal, and a calibration circuit that corrects a discontinuous pulse included in the final output signal based on feedback of the final output signal.

A frequency selecting / switching circuit includes an input terminal, an output terminal, a two-way splitter circuit, a first phase-adjusting circuit, a second phase-adjusting circuit, a first switch, and a second switch. The two-way splitter circuit splits a signal inputted to the input terminal into first and second frequency components and outputs them to its first output end and second output end, respectively. The first output end and second output end of the two-way splitter circuit are connected to a first end of the first phase-adjusting circuit and a first end of the second phase-adjusting circuit, respectively. A second end of the first phase-adjusting circuit and a second end of the second phase-adjusting circuit are connected to the first switch and the second switch, respectively. Each switch switches an output of a signal inputted to its input end, to its output end between a conductive state and a non-conductive state.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

Provided herein are Ising machines having a resonant input mesh driven by a pump signal, a resonant output mesh coupled to the input mesh through a nonlinear component to form a parametric frequency divider (PFD), and the nonlinear component configured to passively activate, responsive to the pump signal exceeding a threshold power, a parametric oscillation between the input and output meshes having an oscillation frequency equal to half an angular input frequency of the pump signal, wherein an output signal of the PFD can be switched between an in-phase state and an out-of-phase state.

This application provides a phased array. The phased array includes: a local oscillator signal adjustment path, a first adder, a first power divider, and a plurality of radio-frequency signal transmit channels. An output end of the local oscillator signal adjustment path is coupled to a first input end of the first adder, and is configured to input a first signal to the first adder. A second input end of the first adder is coupled to a transmit channel, and is configured to receive a second signal, and the first adder superimposes the first signal on the second signal to generate a to-be-transmitted signal. An input end of the first power divider is coupled to an output end of the first adder, an output end of the first power divider is coupled to input ends of the plurality of radio-frequency signal transmit channels, and the first power divider divides the to-be-transmitted signal into a plurality of transmit signals. The plurality of radio-frequency signal transmit channels are configured to process the plurality of transmit signals, and transmit the plurality of transmit signals through a plurality of antennas, so that a local oscillator leakage signal in the phased array can be filtered out while power consumption and a layout area of a communication device are reduced.

A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuity selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.

To provide electronic circuitry and a power converter, capable of suppressing degradation in performance due to transmission of a signal through electromagnetic field coupling.SOLUTION: Electronic circuitry according to the present embodiment includes: a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal on the basis of the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by the electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, on the basis of the first clock signal transmitted by the second electromagnetic field coupler.SELECTED DRAWING: Figure 1

A frequency multiplier, a digital phase-locked loop circuit, and a frequency multiplication method are provided. The frequency multiplier includes: a clock controller, configured to: receive an output signal of a time-to-digital converter in the digital phase-locked loop circuit, and generate a control signal based on a duty cycle error of the output signal; a clock calibration circuit, configured to: receive a reference clock signal, calibrate a duty cycle of the reference clock signal based on the control signal, and output a calibrated clock signal; and a clock frequency multiplier, configured to: receive the calibrated clock signal, multiply a frequency of the calibrated clock signal, and output a frequency multiplied signal to the time-to-digital converter.

A radio-frequency (RF) to direct current (DC) converter is provided. When a DC electrical current is applied via a DC input port of the converter, the DC electrical current is shunted to ground through a Josephson junction (JJ) of the converter and substantially no DC electrical current flows through a resistor of the converter, and when an RF electrical current is applied via an RF input port of the converter, output trains of SFQ current pulses from a DC to SFQ converter of the RF-to-DC converter with pulse-to-pulse spacing inversely proportional to the RF electrical current frequency cause the JJ to switch at a rate commensurate with an RF frequency of the RF electrical current to generate a steady state voltage across the JJ linearly dependent on the RF frequency.

Certain aspects of the present disclosure provide techniques and apparatus for generating oscillating signals and for wireless communication, such as a frequency synthesizer architecture using a step-symmetric inductor. An example frequency synthesizer generally includes an oscillator and a frequency adjustment circuit, an output of the oscillator being coupled to an input of the frequency adjustment circuit, the frequency adjustment circuit comprising a step-symmetric inductive element. An example transceiver generally includes the frequency synthesizer described herein, as well as a mixer having a local-oscillator (LO) input coupled to an output of the frequency adjustment circuit; and an amplifier coupled to the mixer.

A frequency multiplier that has the following characteristics: a phase generator (50, 102) configured to receive an oscillation signal (56) and to provide phase-shifted versions of the oscillation signal (56) at phase generator outputs (60, 62, 64); an injection-synchronized ring oscillator (52, 104) having a plurality of stages (70, 72, 74), wherein each of the phase generator outputs (60, 62, 64) is coupled to a different stage of the plurality of stages (70, 72, 74) for the purpose of multi-point injection, and a combiner (54, 106) configured to combine output signals of the plurality of stages (70, 72, 74) of the injection-synchronized ring oscillator (52, 104) into a signal (78) whose frequency is a multiple of a frequency of the oscillation signal (56).

The invention discloses an SDD high-counting-rate pulse signal processing method, system and device and a medium, and belongs to the field of digital signal processing.The method comprises the steps that pulse charges output by an SDD are read in real time through a transistor reset type pre-amplifier, and original step voltage signals are output according to the pulse charges; acquiring, converting and outputting an original step voltage signal into a first digital signal in real time through a first channel; collecting, converting and outputting the effective voltage signal into a second digital signal in real time through a second channel; wherein the effective voltage signal is obtained by subtracting the bias voltage signal from the original step voltage signal; when the second digital signal is greater than or equal to a first preset threshold value, processing the first digital signal through a bias following algorithm to update a bias voltage signal output by the digital-to-analog converter; and processing the second digital signal output by the second channel in real time through a preset digital signal processing algorithm. According to the invention, the problem of low resolution of an SDD system under a high counting rate can be solved.

The present disclosure relates to a circuit system for frequency multiplication and a signal generation circuit system, in which the circuit system includes: a first set of transistors of a first conductivity type including a first transistor and a second transistor connected in parallel; a second set of transistors of a second conductivity type including a third transistor and a fourth transistor connected in parallel, where the second conductivity type is different from the first conductivity type; wherein the first set of transistors and the second set of transistors are coupled between a first potential and a second potential different from the first potential; wherein a gate of the first transistor and a gate of the third transistor are connected and configured to receive an input signal; and wherein a gate of the second transistor and a gate of the fourth transistor are connected and configured to receive an inverted phase of the input signal.

An electronic device according to an embodiment includes a clock generator generating a first clock signal having a first frequency, and a voltage regulating system configured to receive the first clock signal, receive a detection signal indicating that a boost voltage is within a first voltage range, adjust the first frequency of the first clock signal to generate a second clock signal having a second frequency based on a period during which the detection signal is maintained at a constant level, and generate the boost voltage based on the second clock signal.

A clock doubler includes a first triggering circuit, a second triggering circuit, and a gating circuit. The first triggering circuit generates a first trigger clock signal using rising edges of a first phase clock signal and a second phase clock signal. The second triggering circuit generates a second trigger clock signal using rising edges of a third phase clock signal and a fourth phase clock signal. The gating circuit gates the first and second trigger clock signals to generate an output clock signal the frequency of which is twice the frequency of clock signals provided to the triggering circuits.