210results about "Manipulation for frequency change" patented technology

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

A clock doubler includes a first differential gate and a second differential gate. The first differential gate generates an output clock signal from a first clock signal, a first complementary clock signal, a second clock signal, and a second complementary clock signal and adjusts a duty cycle of the output clock signal based on a first bias control signal. The second differential gate generates a complementary output clock signal from the first clock signal, the first complementary clock signal, the second clock signal, and the second complementary clock signal and adjusts a duty cycle of the complementary output clock signal based on a second bias control signal.

A method may include generating, using an oscillator, a first signal having a frequency based on a current, generating, based on a second signal, a first portion of the current, the first portion of the current having a first frequency characteristic, and generating, based on the second signal, a second portion of the current, the second portion of the current having a second frequency characteristic. A gain of the first frequency characteristic may change based on a frequency of the second signal. The first frequency characteristic may include a first gain at a first frequency, and a second gain at a second frequency. The first gain may be greater than the second gain, and the second frequency may be greater than the first frequency. A phase of the first frequency characteristic may change based on a frequency of the second signal.

The invention relates to a method and system for an injection locked frequency divider with frequency calibration. In some embodiments, a circuit system may include a series of symmetric stages, where an initial stage in the series is coupled to an input signal having a first plurality of phases and an output stage in the series couples an output signal including a second plurality of phases to a calibration engine, wherein a number of the phases in the output signal increases based at least on a number of the symmetric stages and a number of the first plurality of phases in the input signal. Additionally, the circuitry may include embodiments in which the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include embodiments in which the calibration engine outputs a current provided to the series, where the output current may be based at least on a calibration frequency.

A RF generator includes a RF power source configured to generate an output signal at an output frequency, and an extremum-seeking frequency controller configured to generate a frequency control signal. The frequency control signal varies the output frequency of the RF power source, and the frequency control signal is formed from a gradient signal. The RF generator further includes a gradient estimator configured to generate the gradient signal. A frequency of the frequency control signal is adjusted based on the gradient signal. The gradient estimator is configured to receive frequency values of the frequency control signal and corresponding output response values, and the gradient signal is generated based on the frequency values and the output response values. Other example RF generators, methods for extremum-seeking frequency control of a RF generator, and control systems for controlling a RF generator are also disclosed.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.

In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.

The transmitter includes a driver that is connected to an output node and drives the output node with a pulse amplitude modulation-4 (PAM-4) signal having four levels of a most significant bit (MSB) and a least significant bit (LSB), and an equalizer that is connected to the output node and compensates for attenuation of the PAM-4 signal based on a first operating voltage, wherein the equalizer compensates for the attenuation based on applying a second operating voltage having a level greater than a level of the first operating voltage to the output node when a transition from a first level to a second level among the four levels is a rising transition, and compensates for the attenuation based on forming a path for extracting an equalizing current from the output node when the transition from the first level to the second level is a falling transition.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

The microwave pulse generator 101 consists of a logic circuit 203 that outputs pulse data 213 of a set pulse width and amplitude, a frequency generator 201 that outputs sine waves 211, 212 having the same frequency as the selected quantum bit, a RFDAC 204 that converts pulse data 213 into an analogue signal, modulates it with a sine wave 211 and outputs a signal with the frequency of the sine wave as the center frequency as microwave pulse 111, and a frequency divider 202 that outputs system clock 124 divided by the frequency of sine wave 212. The frequency generator 201 operates at the same frequency as the selected quantum bit except when outputting microwave pulse 111, and the logic circuit 203 operates in synchronization with the system clock 124.

A pulse signal multiplier for the provision of a secondary pulse signal without retroactive effect from a primary pulse signal of a pulse signal generator, in particular for the multiplication of speed sensor signals for use in train protection systems, includes an input circuit which taps off the primary pulse signal via a shielded branch signal line, an output circuit which receives the signal transmitted via the potential barrier, and an optical signal transmission path bridging the potential barrier between the input circuit and the output circuit.

According to the present disclosure there is provided a control circuit for a packaged semiconductor chip rail guide tapper driving means, comprising a control signal generator configured to generate control signals at a control frequency, and a drive module arranged to receive the control signals and output drive signals to the driving means based on the control signals to drive a rail guide tapper to tap a rail guide at a tapping frequency corresponding to the control frequency.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

A clock synchronization (SYNC) system. The clock SYNC system comprises a trigger group (110) and a frequency divider group (120); the trigger group (110) comprises N triggers; the frequency divider group (120) comprises N frequency dividers; and the trigger group (110) receives N clock signals and one SYNC pulse signal, respectively transmits the N clock signals to the N frequency dividers, and respectively transmits to the N frequency dividers the N pulse signals outputted by the trigger group (110), wherein N is a positive integer greater than 1.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

A method and device for outputting frequency multiplication signal having high harmonic suppression, and a storage medium. The method includes: obtaining initial signal; inputting the initial signal into target circuit, where the target circuit includes parallel circuit, first circuit of the parallel circuit is provided with frequency multiplier, second circuit of the parallel circuit is provided with phase adjustment module, the first circuit is connected to input end and output ends of the target circuit, the second circuit is disconnected from the input end and the output end, the phase adjustment module is configured to adjust a phase of the second circuit to a target phase, and phase difference between the target phase and a first phase of the first circuit is greater than 90 degrees; taking a target signal output from the target circuit as frequency multiplication signal of the initial signal.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

Systems, apparatuses, and methods for managing power and performance in a computing system. A system management unit detects a condition indicating a change in a power-performance state of a given computing unit is indicated. In response to detecting the indication, the system management unit is configured to initiate a change to a frequency of a clock signal generated by an adaptive oscillator by changing a voltage supplied to the adaptive oscillator. The adaptive oscillator is configured to rapidly change a frequency of the clock signal generated in response to detecting a change in a droopy supply voltage of the adaptive oscillator. The new frequency generated by the adaptive oscillator is based in part on a difference between the droopy supply voltage and a regulated supply voltage of the adaptive oscillator.

An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

The embodiment of the invention discloses a device with a clock signal generator and a method for sampling an input signal. The device comprises a first clock signal generator, a second clock signal generator, an input signal generation circuit and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a functional circuit. The voltage signal generator generates a voltage signal. The functional circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples a value of the voltage signal at a rising edge or a falling edge of the second clock signal and provides the sampled value as an output signal to analyze one or more characteristics of the voltage signal based on the output signal.

A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the SoC, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.