117results about "Manipulation for frequency change" patented technology

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention discloses a clock synchronization system. The clock synchronization system comprises a trigger group and a frequency divider group, the trigger group comprises N triggers, and the frequency divider group comprises N frequency dividers; the trigger group receives N paths of clock signals and one path of SYNC pulse signal, the N paths of clock signals are respectively transmitted to the N frequency dividers, and the N paths of pulse signals output by the trigger group are respectively transmitted to the N frequency dividers, N is a positive integer greater than 1, through the technical scheme of the invention, the risk of generating a metastable state can be reduced, and the power consumption can be reduced at the same time.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

According to the present disclosure there is provided a control circuit for a packaged semiconductor chip rail guide tapper driving means, comprising a control signal generator configured to generate control signals at a control frequency, and a drive module arranged to receive the control signals and output drive signals to the driving means based on the control signals to drive a rail guide tapper to tap a rail guide at a tapping frequency corresponding to the control frequency.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

A clock synchronization (SYNC) system. The clock SYNC system comprises a trigger group (110) and a frequency divider group (120); the trigger group (110) comprises N triggers; the frequency divider group (120) comprises N frequency dividers; and the trigger group (110) receives N clock signals and one SYNC pulse signal, respectively transmits the N clock signals to the N frequency dividers, and respectively transmits to the N frequency dividers the N pulse signals outputted by the trigger group (110), wherein N is a positive integer greater than 1.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

A method and device for outputting frequency multiplication signal having high harmonic suppression, and a storage medium. The method includes: obtaining initial signal; inputting the initial signal into target circuit, where the target circuit includes parallel circuit, first circuit of the parallel circuit is provided with frequency multiplier, second circuit of the parallel circuit is provided with phase adjustment module, the first circuit is connected to input end and output ends of the target circuit, the second circuit is disconnected from the input end and the output end, the phase adjustment module is configured to adjust a phase of the second circuit to a target phase, and phase difference between the target phase and a first phase of the first circuit is greater than 90 degrees; taking a target signal output from the target circuit as frequency multiplication signal of the initial signal.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

Systems, apparatuses, and methods for managing power and performance in a computing system. A system management unit detects a condition indicating a change in a power-performance state of a given computing unit is indicated. In response to detecting the indication, the system management unit is configured to initiate a change to a frequency of a clock signal generated by an adaptive oscillator by changing a voltage supplied to the adaptive oscillator. The adaptive oscillator is configured to rapidly change a frequency of the clock signal generated in response to detecting a change in a droopy supply voltage of the adaptive oscillator. The new frequency generated by the adaptive oscillator is based in part on a difference between the droopy supply voltage and a regulated supply voltage of the adaptive oscillator.

The embodiment of the invention discloses a device with a clock signal generator and a method for sampling an input signal. The device comprises a first clock signal generator, a second clock signal generator, an input signal generation circuit and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a functional circuit. The voltage signal generator generates a voltage signal. The functional circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples a value of the voltage signal at a rising edge or a falling edge of the second clock signal and provides the sampled value as an output signal to analyze one or more characteristics of the voltage signal based on the output signal.

A circuit (12), comprising: frequency multiplier circuitry (120) having input nodes (INp, INN) configured to receive an input signal (Vf0) and an anti-phase version thereof, the input signal (Vf0) having a first frequency value, the frequency multiplier circuitry (120) configured to produce a current signal (i2f0) at a second frequency value that is an even multiple of the first frequency value; a transformer (122) comprising a primary side (Lp, Cp) and a secondary side (Ls, Cs), wherein the primary side (Lp, Cp) of the transformer (122) comprises a primary inductance (Lp) coupled (126) to the frequency multiplier circuitry (120) to receive the current signal (i2f0) therefrom, wherein the secondary side (Ls, Cs) of the transformer (122) is configured to provide a frequency multiplied voltage signal (VOUT); wherein the frequency multiplier circuitry (120) and the transformer (122) are cascaded between at least one first node (D) and a second node (S), the at least one first node (D) and the second node (S) configured to be coupled to a supply node (VDD) and ground (GND); a first shunt resonator (124a) coupled between the supply node (VDD) and the at least one first node (D); a second shunt resonator (124b) coupled between the second node (S) and ground (GND), and a bypass current path (126) coupled between the at least one first node (D) and the second node (S).

A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

The invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency eliminator comprises a plurality of temporary memories, a counter, a control signal generator and a clock pulse gating circuit. At least a portion of the plurality of registers is set to have a value with respect to the plurality of registers. The counter is used for sequentially generating a plurality of count values, the plurality of count values respectively correspond to the at least one part of the temporary register, and the plurality of count values are repeatedly generated. The control signal generator is used for generating a control signal according to the received count value and the value of the corresponding register. The clock gating circuit is used for referring to the control signal to shield or not shield an input clock signal so as to generate an output clock signal.

An example apparatus includes; first current source circuitry (270) having a terminal; a first transistor (275) having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry (200); second current source circuitry (250) having a terminal; a second transistor (260) having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor (296) having a first terminal and a second terminal; a capacitor (292) having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier (265) having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

In an embodiment, a frequency synthesizer includes a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to divide the output clock signal to generate a divided clock signal, a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to generate a gain error signal, and modify the bias control word based on the gain error signal to generate a modified bias control word.

A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.

A pulse signal multiplier for the provision of a secondary pulse signal without retroactive effect from a primary pulse signal of a pulse signal generator, in particular for the multiplication of speed sensor signals for use in train protection systems, includes an input circuit which taps off the primary pulse signal via a shielded branch signal line, an output circuit which receives the signal transmitted via the potential barrier, and an optical signal transmission path bridging the potential barrier between the input circuit and the output circuit.

The present invention relates to a method for setting a system clock of an integrated circuit (1), wherein the integrated circuit (1) has an oscillator module (2) designed to specify a system clock (100) of the integrated circuit (1), a counter module (3), a signal input (4), and a communication interface (5), wherein the method comprises the following steps: a) receiving a reference signal (100) at the signal input (4) for a predefined duration (t), b) incrementing the counter module (3) by one per system clock (100) of the integrated circuit over the duration (t) of the application of the reference signal (200), c) determining a counter value (3a) of the counter module (3) after the duration (t) has elapsed, d) receiving a counter setpoint at the communication interface (5) that corresponds to a number of system clocks during the duration (t) at a setpoint frequency,and e) comparing the counter value (3a) of the counter module (3) with the counter target value and correcting a frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter target value.,

In one embodiment, a frequency synthesizer comprises a digitally controlled oscillator configured to generate an output clock signal based on a digital control word, a clock divider configured to split the output clock signal to generate a split clock signal, a digital-to-digital converter configured to generate a feedback clock signal based on the split clock signal, a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal, a loop filter connected to the time-to-digital converter configured to generate the digital control word based on the phase error signal, and a calibration unit configured to generate a training sequence to produce a gain error signal.and to modify the bias control word based on the gain error signal to create a modified bias control word.

A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.

A method to generate a crystal oscillator clock having a duty cycle via a first stage of a clock circuit, double the crystal oscillator clock and inputting the doubled crystal oscillator clock into a phased-locked loop, feed back a phase-locked loop feedback clock, measure a difference in delay between a first edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock and a second edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock, and adjust the duty cycle of the crystal oscillator clock based on the difference in delay. A device having a detection circuit to measure a difference in delay between first and second edges of a doubled crystal oscillator clock output relative to a phase-locked loop feedback clock, and a controller to adjust the duty cycle of the clock output based on the difference in delay.

Embodiments disclosed herein relate to managing a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing dummy pulses of a clock output. In one example, a system (100) provides a first clock signal (130) via an oscillator (110) and a second clock signal (131) based on the first clock signal (130) and a frequency divider (120). The system 100 further receives a first signal indicative of a change in frequency of the first clock signal (130) from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal (131) and provides a second signal to the oscillator (110) at a time based on the edge of the second clock signal (131) to cause the change to the second frequency.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

A synthesizable clock doubler is disclosed. The clock doubler is implemented using a unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. A replica ring oscillator is used to generate programmable delays to compensate for output clock imperfections, such as cycle-to-cycle variations and double the clock duty cycle.