17results about "Manipulation for frequency change" patented technology

According to the present disclosure there is provided a control circuit for a packaged semiconductor chip rail guide tapper driving means, comprising a control signal generator configured to generate control signals at a control frequency, and a drive module arranged to receive the control signals and output drive signals to the driving means based on the control signals to drive a rail guide tapper to tap a rail guide at a tapping frequency corresponding to the control frequency.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

A frequency multiplier that has the following characteristics: a phase generator (50, 102) configured to receive an oscillation signal (56) and to provide phase-shifted versions of the oscillation signal (56) at phase generator outputs (60, 62, 64); an injection-synchronized ring oscillator (52, 104) having a plurality of stages (70, 72, 74), wherein each of the phase generator outputs (60, 62, 64) is coupled to a different stage of the plurality of stages (70, 72, 74) for the purpose of multi-point injection, and a combiner (54, 106) configured to combine output signals of the plurality of stages (70, 72, 74) of the injection-synchronized ring oscillator (52, 104) into a signal (78) whose frequency is a multiple of a frequency of the oscillation signal (56).

An electronic device according to an embodiment includes a clock generator generating a first clock signal having a first frequency, and a voltage regulating system configured to receive the first clock signal, receive a detection signal indicating that a boost voltage is within a first voltage range, adjust the first frequency of the first clock signal to generate a second clock signal having a second frequency based on a period during which the detection signal is maintained at a constant level, and generate the boost voltage based on the second clock signal.

A clock doubler includes a first triggering circuit, a second triggering circuit, and a gating circuit. The first triggering circuit generates a first trigger clock signal using rising edges of a first phase clock signal and a second phase clock signal. The second triggering circuit generates a second trigger clock signal using rising edges of a third phase clock signal and a fourth phase clock signal. The gating circuit gates the first and second trigger clock signals to generate an output clock signal the frequency of which is twice the frequency of clock signals provided to the triggering circuits.

According to one embodiment, a clock modulation circuit includes a clock output circuit that outputs a clock signal and a multi-divider circuit that has a plurality of frequency division circuits to which the clock signal from the clock output circuit is input. Each frequency division circuit is configured to frequency divide the clock signal. A frequency division control circuit is configured to control a frequency division start time for each of the frequency division circuits and control a phase difference between output signals of at least one pair of frequency division circuits in the plurality of frequency division circuits based on a period of the clock signal.

The application provides a phased array, which comprises: a local oscillator signal adjusting path, a first adder, a first power divider and a plurality of radio frequency signal transmitting channels; the output end of the local oscillator signal adjusting path is coupled with the first input end of the first adder, and is used for inputting a first signal to the first adder; the second input end of the first adder is coupled with the transmitting channels, and is used for receiving a second signal; the first adder superimposes the first signal and the second signal to generate a to-be-transmitted signal; the input end of the first power divider is coupled with the output end of the first adder, the output end of the first power divider is coupled with the input end of the plurality of radio frequency signal transmitting channels, and the first power divider divides the to-be-transmitted signal into a plurality of transmitting signals; and the plurality of radio frequency signal transmitting channels are used for processing the plurality of transmitting signals and transmitting the plurality of transmitting signals through a plurality of antennas, so that the local oscillator leakage signal in the phased array can be filtered out under the condition of reducing the power consumption and the layout area of the communication equipment.

Embodiments provide a clock modulation circuit and a clock modulation method that can measure characteristics of a clock signal with higher accuracy. According to one embodiment, the clock modulation circuit includes a clock output circuit that outputs a clock signal and a multiple frequency divider circuit that has a plurality of frequency divider circuits to which the clock signal from the clock output circuit is input. Each frequency divider circuit is configured to divide the clock signal. A frequency division control circuit is configured to control a frequency division start time of each frequency divider circuit and control a phase difference between output signals of at least a pair of the plurality of frequency divider circuits based on a period of the clock signal.

A synthesizable clock doubler is disclosed. The clock doubler is implemented using a unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. A replica ring oscillator is used to generate programmable delays to compensate for output clock imperfections, such as cycle-to-cycle variations and double the clock duty cycle.

A system comprises an oscillator circuit that includes first and second tuning banks and a current-controlled oscillator. The first tuning bank is connected to a voltage node and receives the tuning signal, generates a voltage drop at the voltage node that corresponds to the tuning signal, and allows the flow of a first current therethrough that varies with the voltage drop. The second tuning bank is connected to the voltage node and receives an oscillator input signal and regulates a second current that flows therethrough in response to a voltage difference between the voltage drop and the oscillator input signal. The current-controlled oscillator receives a third current that is a sum of the first and second currents and fine-tunes an oscillator output signal based on the third current to track a frequency of a reference input signal.

An oscillating signal adjusting circuit is provided. The oscillating signal adjusting circuit is adapted to generate an internal clock signal of a touch and display driver integrated circuit and includes a frequency shift circuit and a spread spectrum control circuit. The frequency shift circuit acquires a first setting data indicated by a mode control signal, and determines whether to shift a frequency of the input clock signal according to the first setting data to generate a first output clock signal. The spread spectrum control circuit to acquires a second setting data indicated by the mode control signal, and determines whether to perform a spreading spectrum operation on the first output clock signal according to the second setting data to generate the internal clock signal. The mode control signal has a first voltage level in a display period and has a second voltage level in a touch sensing period.

A multiple-frequency receiver is disclosed and includes a single voltage-controlled oscillator (VCO) configured to generate an output frequency; a first division circuit configured to divide the output frequency by a first value to generate a first local oscillator (LO) frequency for a first frequency chain; and a second division circuit configured to divide the output frequency by a second value to generate a second LO frequency for a second frequency chain, wherein the first value is different than the second value.

The objective is to provide a clock modulation circuit that can measure the characteristics of a clock with greater precision. [Solution] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.