95results about "Phase shifter" patented technology

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock. The interpolation functions applied to selected pairs of phase vectors can differ to account for integral non-linearity, duty-cycle distortion, phase errors, and crosstalk that vary between phase vectors.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention discloses a W-band switching line MMIC phase shifter based on an aligned CNT Schottky diode. The phase shifter comprises a substrate, a radio frequency input port, a radio frequency output port, two transmission paths with different physical lengths, a switch selection network and a direct current bias circuit. Wherein the switch selection network adopts an aligned carbon nanotube Schottky diode and is configured at the input end and the output end of the transmission path. Complementary control voltage is applied through the direct-current bias circuit, the switch selection network is driven to enable the selected paths to be conducted at the two ends at the same time and the unselected paths to be cut off at the two ends at the same time, and therefore discrete switching of phases is achieved. The high-frequency characteristic of the aligned carbon nanotube device is combined with the double-end complementary selection topology, so that the problem that the amplitude imbalance and the phase precision are difficult to consider at the W wave band is effectively solved, the signal leakage and the parasitic resonance of a non-conducted branch are remarkably inhibited, and the low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss low

One example includes a data alignment system. The system includes a first coupling circuit configured to receive a return-to-zero (RTZ) input pulse and to generate a first single flux quantum (SFQ) pulse in response to the RTZ input pulse being aligned with a phase window of a first clock signal. The system also includes a second coupling circuit configured to receive the RTZ input pulse and to generate a second SFQ pulse in response to the RTZ input pulse being aligned with a phase window of a second clock signal, the first and second clock signals being opposite in phase. The system further includes an alignment circuit that is configured to generate an output SFQ pulse that is aligned to one of the first and second clock signals in response to receiving at least one of the first and second SFQ pulses.

A semiconductor device (10, 20) includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

The invention provides an SYSREF circuit with programmable fine-tuning delay, which relates to the technical field of clock synchronization and comprises an output channel frequency divider, an SYSREF frequency divider, a programmable delay module and a plurality of drivers, the output channel frequency divider and the SYSREF frequency divider are both used for carrying out frequency division processing on a voltage-controlled oscillator signal fvco; the output channel frequency divider and the SYSREF frequency divider are reset through reset pulses, so that phase alignment of output signals of the output channel frequency divider and the SYSREF frequency divider is realized; the output end of the output channel frequency divider is connected with the first driver, and the first driver outputs a system main clock DCLK; the output end of the SYSREF frequency divider outputs a pair of differential signals to be connected with the input end of the programmable delay module, and the output end of the programmable delay module is connected with the input end of the second driver. The method has the advantage of solving the problem that a tiny phase difference still exists after the master clock and the reference clock of the system are synchronized.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

The application provides a radio frequency signal phase shift circuit, a radio frequency signal generating device and a radio frequency power supply equipment, and relates to the technical field of radio frequency. The radio frequency signal phase shift circuit comprises a first phase shift circuit, a second phase shift circuit and a phase shift control unit. The first phase shift circuit is used for moving the phase angle of a radio frequency signal by a first angle to obtain an intermediate phase shift signal and output the intermediate phase shift signal through a first output end. The second phase shift circuit is used for moving the phase angle of the intermediate phase shift signal by a second angle to obtain a target phase shift signal and output the target phase shift signal through a second output end. The phase shift control unit is connected with the first phase shift circuit and the second phase shift circuit. The phase shift control unit is used for determining the first angle and the second angle according to the phase angle of the radio frequency signal, controlling the first phase shift circuit to move the phase angle of the radio frequency signal by the first angle, and controlling the second phase shift circuit to move the phase angle of the intermediate phase shift signal by the second angle. The application can meet the phase angle modulation requirement of the radio frequency signal.

The invention discloses an ultra-wideband silicon-based phase shifter chip working at 0.2-2GHz, which is applied to the technical field of radio frequency microwave integrated circuits. The architecture of the chip consists of a fully differential amplifier, an orthogonal signal generator, a vector synthesis network and a digital-to-analog conversion control circuit. According to the chip, within the working frequency band of 0.2-2 GHz, the phase shifting precision can be 5.625 degrees, the phase shifting range can be 360 degrees, the phase RMS error is smaller than 2.7 degrees, the amplitude RMS error is smaller than 0.6 dB, the input and output return losses are smaller than 12 dB, the gain is larger than-0.5 dB, and the area of the chip is 0.88 mm < 2 >.

This disclosure provides systems, methods, and devices for wireless communications that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communications includes a processing system. The processing system is configured to cause the wireless communication device to: receive a reference signal at a respective input of a plurality of receive chains; process, by each receive chain, the reference signal to generate a respective output signal; determine, for each receive chain, a phase alignment difference between the respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjust a phase alignment of a divider of at least one receive chain of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

Clock phase tuning method including supplying a current (lout) to a capacitor (CL) when first and second clock signals (CK1, CK2) are at a first logic state to generate an voltage (Vout) across the capacitor during a first interval; supplying or drawing a current (lout) to or from the capacitor based on an enable signal when the first and second clock signals are at first and second logic states to generate the voltage across the capacitor during a second interval; drawing a current from the capacitor when the first and second clock signals are at the second logic state to generate the voltage during a third interval; drawing or supplying current from or to the capacitor based on the enable signal when the first and second clock signals are at second and first second logic states to generate the voltage across the capacitor during a fourth interval; and generating a clock signal (Ckout) based on the voltage.

The present invention provides a line-transformer relationship identification system and method. An encoding device is installed on the low-voltage side of a distribution transformer, and a decoding device is installed on each feeder of a switchgear or on a branch line of an adjacent switchgear. A master station is in communication with the encoding and decoding devices. The encoding device encodes acquired transformer terminal unit information, and the decoding device decodes the characteristic vector current signal. The master station issues control instructions to the transformer terminal unit to identify the line-transformer relationship. Line-transformer relationship identification is achieved by first encoding and then decoding the transformer terminal unit information. This simple process significantly improves identification efficiency and accuracy, and facilitates maintenance. The characteristic vector current signal in the present invention has a low frequency, strong distribution transformer penetration, and long transmission distance. The present invention has a simple principle, a small size, low cost, and is easily promoted on a large scale, with a wide range of applications.

The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.

When measuring displacement using the amplitude level of standing waves on a transmission line, the amplitude level of the standing waves follows a curve, and the slope differs depending on the location on the transmission line, resulting in different detection accuracy depending on the location. [Solution] A displacement measurement system characterized by comprising: a first coupler having one end terminated and receiving a first signal from the other end; a second coupler moving in the direction of extension of the first coupler while maintaining a constant distance from the first coupler; a transmitting unit receiving a second signal having the same frequency as the first signal; a receiving unit receiving the signal output from the transmitting unit; a first phase difference detection unit detecting the phase difference between the first signal and the signal output from the second coupler via the first coupler, and the signal output from the receiving unit via the transmitting unit; and a calculation unit calculating the position based on the phase difference information output from the first phase difference detection unit.

Systems and methods for calibrating a clock signal are described. A device can include a processer, a circuit and a system duty cycle control (DCC) circuit. The circuit can perform a first phase shift on a clock signal to generate a first phase-shifted signal. The circuit can perform a second phase shift on the clock signal to generate a second phase-shifted signal. The circuit can perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal. The circuit can sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal. The circuit can sample an output clock signal at a time where the first voltage signal and the second voltage signal overlaps. The processor can generate a digital code based on the output clock signal. The system DCC circuit can calibrate the clock signal using the digital code.

MULTIPHASE SIGNAL GENERATORAn apparatus which includes a multiphase signal generator circuit. The multiphase signal generator circuit is configured to receive as input a complementary analog signal having a fundamental frequency, and generate a plurality of output complementary analog signals. Each output complementary analog signal comprises the same fundamental frequency as the input complementary analog signal, and wherein each output complementary analog signal comprises a different phase.

The invention relates to digital duty cycle calibration. Systems and methods for calibrating a clock signal are described. An apparatus may include a processor, a circuit, and a system duty cycle control (DCC) circuit. The circuit may perform a first phase shift on a clock signal to generate a first phase shifted signal. The circuit may perform a second phase shift on the clock signal to generate a second phase shifted signal. The circuit may perform fixed DCC on the first phase shifted signal to generate a first voltage signal. The circuit may scan the second phase-shifted signal over a duty cycle range to generate a second voltage signal. The circuit may sample the output clock signal at a time when the first voltage signal and the second voltage signal overlap. The processor may generate a digital code based on the output clock signal. The system DCC circuit may use the digital code to calibrate the clock signal.

A phase shifter for a millimeter wave (mmW) communication system, the phase shifter comprising: an in-phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) configured to receive a radio frequency (RF) signal, the I VGA and the Q VGA configured to provide selectable outputs to a primary side of a first electromagnetic (EM) element and a primary side of a second EM element, respectively, the first EM element is configured to provide a single-ended I output and the second EM element is configured to provide a single-ended Q output; and a hybrid quadrature generator (HQG) configured to receive a single-ended I output of the first EM element and a single-ended Q output of the second EM element, the HQG configured to provide a combined signal at a desired phase.

A frequency selecting / switching circuit includes an input terminal, an output terminal, a two-way splitter circuit, a first phase-adjusting circuit, a second phase-adjusting circuit, a first switch, and a second switch. The two-way splitter circuit splits a signal inputted to the input terminal into first and second frequency components and outputs them to its first output end and second output end, respectively. The first output end and second output end of the two-way splitter circuit are connected to a first end of the first phase-adjusting circuit and a first end of the second phase-adjusting circuit, respectively. A second end of the first phase-adjusting circuit and a second end of the second phase-adjusting circuit are connected to the first switch and the second switch, respectively. Each switch switches an output of a signal inputted to its input end, to its output end between a conductive state and a non-conductive state.

In an example, a circuit includes clock data recovery (CDR) circuitry having an input and an output. The circuit also includes a delay circuit having an input coupled to the output of the CDR circuitry, and having an output. The circuit includes a multi-phase oscillator having an input coupled to the output of the delay circuit, and having an output. The circuit also includes a divider having an input coupled to the output of the multi-phase oscillator, and having an output coupled to the input of the CDR circuitry.

The invention discloses a multi-phase clock signal output circuit and a control method thereof. The multi-phase clock signal output circuit comprises at least two clock signal output links; and each clock signal output link comprises a phase selection module, a phase conversion module and a delay module. A plurality of input ends of the phase selection module are electrically connected with a plurality of clock signal input ends in a one-to-one correspondence manner, the input end of the phase selection module is used as the input end of an output link of clock signals, and the output end of the phase selection module is electrically connected with the input end of the phase conversion module; and the phase selection module is used for selecting an input clock signal. The output end of the phase conversion module is electrically connected with the input end of the time delay module, the phase conversion module is used for inverting the phase of the clock signal, and the time delay module is used for adjusting the phase of the clock signal. According to the invention, large-range and high-precision clock signal output is realized.

This application provides a phased array. The phased array includes: a local oscillator signal adjustment path, a first adder, a first power divider, and a plurality of radio-frequency signal transmit channels. An output end of the local oscillator signal adjustment path is coupled to a first input end of the first adder, and is configured to input a first signal to the first adder. A second input end of the first adder is coupled to a transmit channel, and is configured to receive a second signal, and the first adder superimposes the first signal on the second signal to generate a to-be-transmitted signal. An input end of the first power divider is coupled to an output end of the first adder, an output end of the first power divider is coupled to input ends of the plurality of radio-frequency signal transmit channels, and the first power divider divides the to-be-transmitted signal into a plurality of transmit signals. The plurality of radio-frequency signal transmit channels are configured to process the plurality of transmit signals, and transmit the plurality of transmit signals through a plurality of antennas, so that a local oscillator leakage signal in the phased array can be filtered out while power consumption and a layout area of a communication device are reduced.