64results about "Phase shifter" patented technology

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention discloses a W-band switching line MMIC phase shifter based on an aligned CNT Schottky diode. The phase shifter comprises a substrate, a radio frequency input port, a radio frequency output port, two transmission paths with different physical lengths, a switch selection network and a direct current bias circuit. Wherein the switch selection network adopts an aligned carbon nanotube Schottky diode and is configured at the input end and the output end of the transmission path. Complementary control voltage is applied through the direct-current bias circuit, the switch selection network is driven to enable the selected paths to be conducted at the two ends at the same time and the unselected paths to be cut off at the two ends at the same time, and therefore discrete switching of phases is achieved. The high-frequency characteristic of the aligned carbon nanotube device is combined with the double-end complementary selection topology, so that the problem that the amplitude imbalance and the phase precision are difficult to consider at the W wave band is effectively solved, the signal leakage and the parasitic resonance of a non-conducted branch are remarkably inhibited, and the low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss high-isolation low-insertion-loss low

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

The application provides a radio frequency signal phase shift circuit, a radio frequency signal generating device and a radio frequency power supply equipment, and relates to the technical field of radio frequency. The radio frequency signal phase shift circuit comprises a first phase shift circuit, a second phase shift circuit and a phase shift control unit. The first phase shift circuit is used for moving the phase angle of a radio frequency signal by a first angle to obtain an intermediate phase shift signal and output the intermediate phase shift signal through a first output end. The second phase shift circuit is used for moving the phase angle of the intermediate phase shift signal by a second angle to obtain a target phase shift signal and output the target phase shift signal through a second output end. The phase shift control unit is connected with the first phase shift circuit and the second phase shift circuit. The phase shift control unit is used for determining the first angle and the second angle according to the phase angle of the radio frequency signal, controlling the first phase shift circuit to move the phase angle of the radio frequency signal by the first angle, and controlling the second phase shift circuit to move the phase angle of the intermediate phase shift signal by the second angle. The application can meet the phase angle modulation requirement of the radio frequency signal.

This disclosure provides systems, methods, and devices for wireless communications that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communications includes a processing system. The processing system is configured to cause the wireless communication device to: receive a reference signal at a respective input of a plurality of receive chains; process, by each receive chain, the reference signal to generate a respective output signal; determine, for each receive chain, a phase alignment difference between the respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjust a phase alignment of a divider of at least one receive chain of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

Clock phase tuning method including supplying a current (lout) to a capacitor (CL) when first and second clock signals (CK1, CK2) are at a first logic state to generate an voltage (Vout) across the capacitor during a first interval; supplying or drawing a current (lout) to or from the capacitor based on an enable signal when the first and second clock signals are at first and second logic states to generate the voltage across the capacitor during a second interval; drawing a current from the capacitor when the first and second clock signals are at the second logic state to generate the voltage during a third interval; drawing or supplying current from or to the capacitor based on the enable signal when the first and second clock signals are at second and first second logic states to generate the voltage across the capacitor during a fourth interval; and generating a clock signal (Ckout) based on the voltage.

The present invention provides a line-transformer relationship identification system and method. An encoding device is installed on the low-voltage side of a distribution transformer, and a decoding device is installed on each feeder of a switchgear or on a branch line of an adjacent switchgear. A master station is in communication with the encoding and decoding devices. The encoding device encodes acquired transformer terminal unit information, and the decoding device decodes the characteristic vector current signal. The master station issues control instructions to the transformer terminal unit to identify the line-transformer relationship. Line-transformer relationship identification is achieved by first encoding and then decoding the transformer terminal unit information. This simple process significantly improves identification efficiency and accuracy, and facilitates maintenance. The characteristic vector current signal in the present invention has a low frequency, strong distribution transformer penetration, and long transmission distance. The present invention has a simple principle, a small size, low cost, and is easily promoted on a large scale, with a wide range of applications.

When measuring displacement using the amplitude level of standing waves on a transmission line, the amplitude level of the standing waves follows a curve, and the slope differs depending on the location on the transmission line, resulting in different detection accuracy depending on the location. [Solution] A displacement measurement system characterized by comprising: a first coupler having one end terminated and receiving a first signal from the other end; a second coupler moving in the direction of extension of the first coupler while maintaining a constant distance from the first coupler; a transmitting unit receiving a second signal having the same frequency as the first signal; a receiving unit receiving the signal output from the transmitting unit; a first phase difference detection unit detecting the phase difference between the first signal and the signal output from the second coupler via the first coupler, and the signal output from the receiving unit via the transmitting unit; and a calculation unit calculating the position based on the phase difference information output from the first phase difference detection unit.

MULTIPHASE SIGNAL GENERATORAn apparatus which includes a multiphase signal generator circuit. The multiphase signal generator circuit is configured to receive as input a complementary analog signal having a fundamental frequency, and generate a plurality of output complementary analog signals. Each output complementary analog signal comprises the same fundamental frequency as the input complementary analog signal, and wherein each output complementary analog signal comprises a different phase.

A phase shifter for a millimeter wave (mmW) communication system, the phase shifter comprising: an in-phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) configured to receive a radio frequency (RF) signal, the I VGA and the Q VGA configured to provide selectable outputs to a primary side of a first electromagnetic (EM) element and a primary side of a second EM element, respectively, the first EM element is configured to provide a single-ended I output and the second EM element is configured to provide a single-ended Q output; and a hybrid quadrature generator (HQG) configured to receive a single-ended I output of the first EM element and a single-ended Q output of the second EM element, the HQG configured to provide a combined signal at a desired phase.

A frequency selecting / switching circuit includes an input terminal, an output terminal, a two-way splitter circuit, a first phase-adjusting circuit, a second phase-adjusting circuit, a first switch, and a second switch. The two-way splitter circuit splits a signal inputted to the input terminal into first and second frequency components and outputs them to its first output end and second output end, respectively. The first output end and second output end of the two-way splitter circuit are connected to a first end of the first phase-adjusting circuit and a first end of the second phase-adjusting circuit, respectively. A second end of the first phase-adjusting circuit and a second end of the second phase-adjusting circuit are connected to the first switch and the second switch, respectively. Each switch switches an output of a signal inputted to its input end, to its output end between a conductive state and a non-conductive state.

The invention discloses a multi-phase clock signal output circuit and a control method thereof. The multi-phase clock signal output circuit comprises at least two clock signal output links; and each clock signal output link comprises a phase selection module, a phase conversion module and a delay module. A plurality of input ends of the phase selection module are electrically connected with a plurality of clock signal input ends in a one-to-one correspondence manner, the input end of the phase selection module is used as the input end of an output link of clock signals, and the output end of the phase selection module is electrically connected with the input end of the phase conversion module; and the phase selection module is used for selecting an input clock signal. The output end of the phase conversion module is electrically connected with the input end of the time delay module, the phase conversion module is used for inverting the phase of the clock signal, and the time delay module is used for adjusting the phase of the clock signal. According to the invention, large-range and high-precision clock signal output is realized.

This application provides a phased array. The phased array includes: a local oscillator signal adjustment path, a first adder, a first power divider, and a plurality of radio-frequency signal transmit channels. An output end of the local oscillator signal adjustment path is coupled to a first input end of the first adder, and is configured to input a first signal to the first adder. A second input end of the first adder is coupled to a transmit channel, and is configured to receive a second signal, and the first adder superimposes the first signal on the second signal to generate a to-be-transmitted signal. An input end of the first power divider is coupled to an output end of the first adder, an output end of the first power divider is coupled to input ends of the plurality of radio-frequency signal transmit channels, and the first power divider divides the to-be-transmitted signal into a plurality of transmit signals. The plurality of radio-frequency signal transmit channels are configured to process the plurality of transmit signals, and transmit the plurality of transmit signals through a plurality of antennas, so that a local oscillator leakage signal in the phased array can be filtered out while power consumption and a layout area of a communication device are reduced.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

A system includes a first coupler having one end portion terminated that receives a first signal input from another end portion, a second coupler that moves in a direction in which the first coupler extends while maintaining a certain distance from the first coupler, a transmission unit that receives a second signal having a frequency same as a frequency of the first signal and transmit a signal, a reception unit that receives the signal output from the transmission unit, a detection unit that detects a phase difference between a signal output from the second coupler via the first coupler based on the first signal and a signal output from the reception unit via the transmission unit based on the second signal, and a calculation unit that calculates a position based on information of the phase difference output from the detection unit.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

To provide electronic circuitry and a power converter, capable of suppressing degradation in performance due to transmission of a signal through electromagnetic field coupling.SOLUTION: Electronic circuitry according to the present embodiment includes: a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal on the basis of the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by the electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, on the basis of the first clock signal transmitted by the second electromagnetic field coupler.SELECTED DRAWING: Figure 1

A phase shifter for a millimeter wave (mmW) communication system including an in phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) configured to receive radio frequency (RF) signals, the I VGA and the Q VGA configured to provide a selectable output to primary sides of first and second electromagnetic (EM) elements, respectively, the first EM element configured to provide a single-ended I output and the second EM element configured to provide a single-ended Q output, and a hybrid quadrature generator (HQG) configured to receive the single-ended I output of the first EM element and the single-ended Q output of the second EM element, the HQG configured to provide a combined signal at a desired phase.

The application discloses an alternating current energy detection device, a voltage detection unit, a coupling capacitor formed by being coupled with a measured cable, a first voltage obtained based on an actual voltage and the coupling capacitor, and the first voltage output to a data processing unit; a current detection unit, a measured cable current detected and output to the data processing unit; the data processing unit, the first voltage and the measured cable current received, a first voltage value and a measured cable current value determined; a product of the first voltage value and a measured cable voltage amplification multiple calculated, a measured cable voltage value determined; and the measured cable voltage value and the measured cable current value used to calculate the energy transmitted on the measured cable. The device provided by the application can avoid the installation position of the detection device limited to an electrical connection point, and there is no electrical connection between the detection device and the measured cable. On the premise that the amplitude and phase of the measured voltage and all harmonic information of the measured cable are detected in real time, the safety level of the detection device can be improved, and the cost can be reduced.

The invention provides a phase shift circuit of an optical encoder. The phase shift circuit receives a first signal, a second signal, a third signal and a fourth signal which have a 90-degree phase difference in sequence, and comprises a resistor string and an attenuation circuit. And the resistor string is used for correcting phases of the first signal, the second signal, the third signal and the fourth signal. And the attenuation circuit is used for enabling the phase-corrected signals output by the resistor string to have the same amplitude.

A wireless power transfer secondary or pick-up has a resonant circuit and a switch connected to the resonant circuit operable to produce a phase shift in an oscillating voltage or current in the resonant circuit. A controller is configured to operate the switch to introduce one or more controlled phase shifts in the oscillating voltage or current in the resonant circuit which encode data for detection by a coupled circuit.

Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system further includes control logic configured to: (1) at least partially discharge a first pre-charged capacitive load in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load in response to a reference signal associated with the phase interpolator. The system further includes a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, where the feedback is dependent on a first voltage provided by the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load.

This disclosure provides systems, methods, and devices for wireless communication that support enhanced phase calibration operations. In a first aspect, an apparatus for wireless communication includes a processing system. The processing system is configured to cause the wireless communication device to: receive reference signals at respective inputs of the plurality of receive chains; processing the reference signal by each receive chain to generate a respective output signal; determining, for each receive chain, a phase alignment difference between a respective output signal of the receive chain and a reference output signal of a reference receive chain of the plurality of receive chains; and adjusting a phase alignment of a frequency divider of at least one of the plurality of receive chains based on the determined phase alignment difference for the at least one receive chain. Other aspects and features are also claimed and described.

An embodiment is a phase adjustment circuit includes a sine wave output circuit, a first multiplier, a second multiplier, and an adder. The sine wave output circuit is configured to output two sine wave signals of a fixed phase difference. The first multiplier is configured to multiply an amplitude of a first sine wave signal output from the sine wave output circuit by a first variable to generate a first output signal. The second multiplier is configured to multiply an amplitude of a second sine wave signal output from the sine wave output circuit by a second variable to generate a second output signal. The adder is configured to add the first output signal from the first multiplier and the second output signal from the second multiplier.

The invention relates to a clock phase calibration device, a clock phase calibration method and a chip. The clock phase calibration device comprises a clock management module, a phase analysis module and a phase interpolator. The signal input end of the clock management module is used for receiving a clock signal, the output end of the clock management module is connected with the input end of the phase analysis module and the input end of the phase interpolator, and the output end of the phase analysis module is connected with the control end of the clock management module; the phase analysis module is used for generating a phase adjustment control code of the clock signal according to the in-phase clock signal and the orthogonal clock signal output by the clock management module; the clock management module is used for adjusting the phase between the in-phase clock signal and the orthogonal clock signal according to the phase adjustment control code to obtain a phase adjustment clock signal; and the phase interpolator is used for generating and outputting a calibration clock signal of the clock signal according to the phase adjustment clock signal. By adopting the device, the calibration effect of the clock phase calibration device can be improved.