Ultra-wideband silicon-based phase shifter chip working at 0.2-2GHz

Abstract

The invention discloses an ultra-wideband silicon-based phase shifter chip working at 0.2-2GHz, which is applied to the technical field of radio frequency microwave integrated circuits. The architecture of the chip consists of a fully differential amplifier, an orthogonal signal generator, a vector synthesis network and a digital-to-analog conversion control circuit. According to the chip, within the working frequency band of 0.2-2 GHz, the phase shifting precision can be 5.625 degrees, the phase shifting range can be 360 degrees, the phase RMS error is smaller than 2.7 degrees, the amplitude RMS error is smaller than 0.6 dB, the input and output return losses are smaller than 12 dB, the gain is larger than-0.5 dB, and the area of the chip is 0.88 mm < 2 >.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency and microwave integrated circuits, and particularly relates to a phase shifter chip. Background Art

[0002] Since the birth of phased array technology, with its unique beam control ability and flexibility, it has shown extensive application potential in many high-tech fields. This technology controls the phase of each unit in the array electronically, thereby achieving precise control of the beam direction, shape, and intensity, greatly improving the performance and efficiency of systems such as radar detection, communication transmission, meteorological observation, and remote sensing monitoring. In a phased array system, the phase shifter, as a key device, can accurately change the phase of a signal according to the system requirements, thereby realizing flexible adjustment of the beam. In a phased array radar, the role of the phase shifter is particularly important. By precisely controlling the phase of the signal of each antenna unit, the phase shifter can achieve rapid scanning and pointing of the beam without physically moving the antenna, thus greatly improving the scanning speed and flexibility of the radar. In addition, the phase shifter can also achieve rapid change of the antenna beam shape. By precisely controlling the antenna beam shape, the signal energy can be reasonably distributed and the anti-interference ability of the system can be improved. The phase shifter also plays an important role in fields such as wireless communication and satellite communication. In a wireless communication system, the phase shifter can be used to optimize the signal path, improve the data transmission rate, and reduce errors. In a satellite communication system, the phase shifter can be used to achieve multi-beam signal output, enhancing the measurement accuracy and coverage of the system. With the development of modern communication technology, phased array technology has received increasing attention, and the application of phase shifters in it has become more and more extensive. The performance requirements for phase shifters will also be getting higher and higher. Research and development of phase shifters with characteristics such as ultra-wideband, low insertion loss, and low phase shift error will become an important topic. Summary of the Invention

[0003] To solve the above technical problems, the present invention proposes an ultra-wideband silicon-based phase shifter chip operating at 0.2 - 2 GHz.

[0004] The technical solution adopted by the present invention is: an ultra-wideband silicon-based phase shifter chip operating at 0.2 - 2 GHz, including: a fully differential amplifier, a quadrature signal generator, a vector synthesis network, and a digital-to-analog conversion control circuit;

[0005] The fully differential amplifier is used to amplify the two input differential signals, and the two amplified differential signals are denoted as Vin+ and Vin-; Vin+ and Vin are used as the inputs of the quadrature signal generator;

[0006] The quadrature signal generator converts Vin+ and Vin into four quadrature signals VI+, VI-, VQ+, and VQ-; VI+ and VI- are denoted as the I-channel quadrature signals, and VQ+ and VQ- are denoted as the Q-channel quadrature signals;

[0007] The vector synthesis network synthesizes the I-channel quadrature signal and the Q-channel quadrature signal into a differential signal with a certain phase shift value;

[0008] The digital-to-analog conversion control circuit is used to control the tail current of the vector synthesis network.

[0009] Advantages of the present invention: The present invention designs an ultra-wideband 6-bit phase shifter chip operating at 0.2 - 2 GHz. By adding an additional differential amplifier circuit as a gain compensation circuit at the differential input of the quadrature signal generator, the chip provides good input matching. Specifically, the first-stage current amplifier is designed with a current mirror structure. By adjusting the resistance value of resistor R1, the magnitude of the reference current is controlled, thereby controlling the gain of the first-stage amplifier. By adjusting the resistance values of resistors R2 and R3, the input matching is achieved. By adjusting the resistance values of resistors R4 and R5, the output voltage magnitude is controlled; The chip of the present invention adopts a four-stage RC polyphase filter structure to achieve low phase shift error within a wide frequency band, realizing low phase shift error, low insertion loss, and high-precision phase shift function within the 0.2 - 2 GHz frequency band; Specifically, the chip of the present invention can achieve a phase shift accuracy of 5.625°, a phase shift range of 360°, a phase RMS error of less than 2.7°, an amplitude RMS error of less than 0.6 dB, input and output return losses of less than 12 dB, a gain of greater than -0.5 dB, and a chip area of 0.88 mm 2 。 Description of the Drawings

[0010] Figure 1 It is the schematic diagram of the overall architecture of the phase shifter.

[0011] Figure 2 It is the circuit diagram of the first stage of the fully differential amplifier.

[0012] Figure 3 It is the circuit diagram of the second stage of the fully differential amplifier.

[0013] Figure 4 It is the circuit diagram of the quadrature signal generator.

[0014] Figure 5 It is the circuit diagram of the vector synthesis network.

[0015] Figure 6 It is the circuit diagram of the digital-to-analog conversion control.

[0016] Figure 7 It is the post-simulation result diagram of the relative phase of the phase shifter.

[0017] Figure 8 It is the post-simulation result diagram of the gain of the phase shifter.

[0018] Figure 9This is the post-simulation result graph of the input return loss of the phase shifter.

[0019] Figure 10 This is the post-simulation result graph of the output return loss of the phase shifter.

[0020] Figure 11 This is the post-simulation result graph of the phase RMS error of the phase shifter.

[0021] Figure 12 This is the post-simulation result graph of the amplitude RMS error of the phase shifter. Detailed implementation manner

[0022] To facilitate the understanding of the technical content of the present invention by those skilled in the art, the following further explains the content of the present invention in conjunction with the accompanying drawings.

[0023] The present invention designs an ultra-wideband phase shifter chip operating at 0.2 - 2 GHz based on the SMIC 55nm CMOS process. The architecture of this chip consists of a fully differential amplifier, a quadrature signal generator, a vector synthesis network, and a digital-to-analog conversion control circuit. This chip can achieve a phase shift accuracy of 5.625°, a phase shift range of 360°, a phase RMS error of less than 2.7°, an amplitude RMS error of less than 0.6 dB, input and output return losses of less than 12 dB, a gain of greater than -0.5 dB, and a chip area of 0.88 mm 2 .

[0024] The technical solution adopted by the present invention is: an ultra-wideband silicon-based phase shifter chip operating at 0.2 - 2 GHz. The specific architecture of this chip is as Figure 1 shown, including: a fully differential amplifier, a quadrature signal generator, a vector synthesis network, and a digital-to-analog conversion control circuit.

[0025] Among them:

[0026] (1) Considering that passive circuits such as the quadrature signal generator will introduce a certain insertion loss, and although the vector modulation circuit has a certain gain, its main function is to perform amplitude modulation on the quadrature signal and synthesize to achieve phase shift, and its gain is relatively limited. Therefore, in order to compensate for the overall insertion loss of the circuit, a differential amplifier circuit is additionally added at the differential input end of the quadrature signal generator as a gain compensation circuit. The differential output end of the fully differential amplifier is connected to the differential input end of the subsequent quadrature signal generator. The fully differential amplifier has the advantages of high common-mode rejection ratio, high input impedance, and low phase shift error.

[0027] The designed fully differential amplifier consists of two stages. The first stage is a current amplifier, and the second stage is a common-source differential amplifier with a common-mode feedback network.

[0028] As Figure 2As shown, the current amplifier is designed with a current mirror structure. By adjusting the resistance value of resistor R1, the magnitude of the reference current is controlled, thereby controlling the gain of the first-stage amplifier. By adjusting the resistance values of resistors R2 and R3, input matching is achieved. By adjusting the resistance values of resistors R4 and R5, the magnitude of the output voltage is controlled. Figure 2 In it, Vin+ is connected to the gate and drain of M1 and the gate of M3, and Vin- is connected to the gate and drain of M2 and the gate of M2.

[0029] As Figure 3 shown, the second-stage amplifier is a common-source differential amplifier with a common-mode feedback network. Resistor R8 is the source negative feedback resistor. When the product of the transconductance gm of MOS transistors M9 and M10 and the source resistor R8 (much greater than 1) is large enough, the gain is the ratio of the load resistor to the source resistor R8. The load resistor mentioned here specifically is: as Figure 3 shown, the parallel combination of MOS transistors M7 and M8 and resistors R6 and R7 as a whole serves as the load resistor. Capacitor C1 is the source degeneration capacitor, and a zero point is constructed through the RC parallel network to expand the bandwidth. The common-mode feedback network adopts a double differential pair structure, without internal resistors or capacitors, and the impedance of each node is relatively small, so the open-loop unity-gain bandwidth is relatively large. The M13 and M14 branches of the common-mode feedback circuit respectively provide current biasing for the two differential pair circuits, detect the two output voltages Vout+ and Vout- of the fully differential from the gate terminals of M15 and M18 respectively, and compare them with the voltage Vcm at the gate terminals of M16 and M17. Vcm is the expected value of the externally applied output common-mode level. The amplified voltage is fed back to the gate terminals of M7 and M8 from the diode-connected M13 transistor to adjust the active load terminal, thereby stabilizing the output common-mode voltage at Vcm. The common-mode feedback structure stabilizes the output common-mode level and the static operating point of the circuit, thereby stabilizing the gain of the amplifier.

[0030] Figure 3 In it, the drain of M9 is connected to the gate of M15, and the drain of M10 is connected to the gate of M18; Figure 3 In it, Vin+ and Vin- are Figure 2 the output voltages of the current amplifier in Figure 2 corresponding to Vout+ and Vout- in Figure 3 In it, VB is the gate bias voltage of MOS transistors M11, M12, M19, and M20, used to control the four MOS transistors to be in the saturation region.

[0031] (2) The circuit diagram of the quadrature signal generator is as Figure 4As shown in the figure. The function of the circuit is to convert two input differential signals Vin+ and Vin- into four quadrature signals VI+, VI-, VQ+ and VQ-. The circuit structure is a type-II four-stage RC polyphase filter network, which uses the phase difference between the output signals of the RC low-pass circuit and the CR high-pass circuit to generate quadrature signals. Each stage of the type-II four-stage RC polyphase filter is formed by connecting four groups of RC series circuits end to end. The resistance and capacitance values of each group are the same, namely R9, R10, R11, R12 and C2, C3, C4, C5. The two ends of the four resistors in each stage are used as the input and output terminals of the four signals. The input terminals of the four resistors in the subsequent stage are respectively connected to the output terminals of the resistors in the previous stage. Among them, the two input terminals of the four resistors in the first-stage circuit are respectively connected to the two differential signals. The quadrature signals generated by this circuit have equal amplitudes in the full frequency band, and the phases differ exactly by 90° only at frequencies 1 / R9C2, 1 / R10C3…1 / RnCn. By cascading a four-stage polyphase filter network, poles are added in the frequency band to expand the bandwidth.

[0032] (3) The vector synthesis circuit diagram is as shown in Figure 5 As shown in the figure. The function of the circuit is to select two quadrature signals for vector synthesis into a differential signal with a certain phase shift value. The vector synthesis network adopts the architecture of an analog multiplier module with two Gilbert cells sharing the same load. Two Gilbert cells are respectively fed with the I-channel and Q-channel quadrature signals. Among them, the I-channel quadrature signals VI+ and VI- are respectively input to the gates of the two differential pairs of transistors M24, M25 and M23, M26. The Q-channel quadrature signals VQ+ and VQ- are respectively input to the gates of the two differential pairs of transistors M28, M29 and M27, M30. The sources of each differential pair are connected to the drains of the two bottom differential pairs of transistors M31, M32 and M33, M34, and are respectively connected to transistors M35 and M36. The four gate bias voltages VgI, VgQ, VmI, and VmQ are provided by the subsequent digital-to-analog conversion control circuit in the form of a cascode current mirror. By switching the switches SI and SQ, and control to achieve that only one pair of differential pairs in the I and Q channel Gilbert cells works at the same time, thereby selecting the quadrant range corresponding to the generated signal. Taking the I-channel Gilbert cell as an example, when the SI switch is closed, the gate of transistor M31 is connected to VgI and thus conducts, and the tail current of transistor M35 flows into this differential pair. The two input quadrature voltage signals VI+ and VI- are converted into current signals through the two amplifying transistors M23 and M24. The I-channel current signal is vector synthesized with the Q-channel signal selected by the SQ switch through the active loads M21 and M22 transistors shared by the I and Q channels to output two differential voltage signals Vout+ and Vout- with specific phase shift values.

[0033] For example, Figure 5 the SI and SQ switches in Figure 5The M35 and M31 tubes, and the M36 and M34 tubes in it are respectively connected to Figure 6 The M60, M59 and M62, M61 tubes in it form two sets of cascode current mirrors, so Figure 5 the tail current of the circuit is generated by Figure 6 the tail current of the circuit is replicated. Figure 6 The currents of the six-way cascode current mirrors in the circuit are replicated from the constant reference current generated by the resistor R15. Therefore, the current magnitude of each path is constant. The six-way currents all flow into the two-way cascode circuits composed of the M60, M59 and M62, M61 tubes. Therefore, the sum of their tail currents remains unchanged. The sum of the two-way tail currents of the Figure 5 circuit replicated by this current mirror also remains unchanged.

[0034] As long as the sum of the tail currents of the circuit remains unchanged, the gain of the vector synthesis module remains unchanged. By adjusting the ratio of the two-way tail currents, the phase value of the circuit can be controlled; specifically, by switching Figure 6 the switches S1, S2... S6 in it to control the currents of the six-way cascode current mirrors to flow into the two-way cascode circuits composed of the M60, M59 or M62, M61 tubes respectively to adjust the magnitudes of the two-way tail currents. The magnitudes of the two-way tail currents of the Figure 5 circuit replicated by this current mirror also change accordingly. Therefore, this structure has a relatively high phase shift accuracy and can maintain a relatively stable gain.

[0035] (4) The digital-to-analog conversion control circuit is as Figure 6 shown. The function of this circuit is to control the magnitudes of the I and Q two-way tail currents of the input vector adder in the form of a numerically controlled switch controlling a current mirror array to control the phase shift angle. The circuit uses cascode current mirrors to achieve 6-bit numerical control. The current generated by the resistor R15 is replicated into the PMOS cascode current mirrors M39 and M40 tubes by the NMOS current mirrors M37 and M38 tubes as the reference current. The other six groups of current mirror structures are the same. By changing the gate lengths of each group of three MOS tubes in proportion, the current value of each group of current mirrors is 2 N times that of the reference current.

[0036] The control current principles of the six groups of current mirrors are the same. Taking the group of current mirrors where transistors M41, M42, and M43 are located as an example, the gate of transistor M43 is connected to the gate of transistor M40, and the source is connected to the drains of transistors M41 and M42. The sources of transistors M41 and M42 are respectively connected to the transistors M61, M62 and M59, M60 of two groups of cascode current mirrors. By controlling switch S1, the gates of transistors M41 and M42 are respectively connected to high level and the gate of transistor M39, so that one of the two MOS transistors forms a cascode current mirror with transistors M43, M39, and M40 to replicate the current according to a certain ratio, and the other transistor is cut off. The conducting MOS transistor controls the current of this path to flow into transistors M59, M60 or M61, M62. The gates of transistors M59, M60 or M61, M62 are respectively connected to the gates of the two groups of cascode structures of transistors M31 or M32 and M35, and transistors M33 or M34 and M36 in the above-mentioned vector synthesis network, that is, the gates VgI, VgQ, VmI, and VmQ of the four MOS transistors in the two circuits are respectively connected, forming two groups of cascode current mirrors, so that the two paths of current output by the digital-to-analog conversion control circuit flow into transistors M35 and M36 of the vector synthesis network as tail currents. The six groups of current mirror arrays control each group of currents to flow into the I path or the Q path through switches S1, S2... S6, ensuring that the total current of the vector synthesis network remains unchanged while the current values of the I and Q paths are controlled by a 6-bit digital control switch to achieve the phase shift effect.

[0037] As Figure 7 shown, within the operating frequency band of 0.2 - 2 GHz, the phase shift accuracy of the phase shifter of the present invention is 5.625°, and the phase shift range is 360°. As Figure 8 shown, within the operating frequency band of 0.2 - 2 GHz, the gain of the phase shifter of the present invention is greater than -0.5 dB. As Figure 9 、 Figure 10 shown, within the operating frequency band of 0.2 - 2 GHz, the input and output return losses of the phase shifter of the present invention are both less than 12 dB. As Figure 11 shown, within the operating frequency band of 0.2 - 2 GHz, the phase RMS error of the phase shifter of the present invention is less than 2.7°. As Figure 12 shown, within the operating frequency band of 0.2 - 2 GHz, the amplitude RMS error of the phase shifter of the present invention is less than 0.6 dB.

[0038] Those of ordinary skill in the art will realize that the examples described here are to help readers understand the principles of the present invention and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, various changes and modifications can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. An ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz, characterized in that: include: Fully differential amplifier, orthogonal signal generator, vector synthesis network, digital-to-analog conversion control circuit; The fully differential amplifier is used to amplify the two differential signals inputted. The two differential signals after amplification are recorded as Vin+ and Vin-. Vin+ and Vin- are used as the inputs of the orthogonal signal generator. The orthogonal signal generator converts Vin+ and Vin- into four orthogonal signals VI+, VI-, VQ+ and VQ-; VI+ and VI- are recorded as I-channel orthogonal signals, and VQ+ and VQ- are recorded as Q-channel orthogonal signals; The vector synthesis network synthesizes the I-channel orthogonal signal and the Q-channel orthogonal signal into a differential signal with a certain phase shift value; The digital-to-analog conversion control circuit is used to control the tail current of the vector synthesis network.

2. The ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz according to claim 1, characterized in that: The fully differential amplifier includes a first-stage current amplifier and a second-stage common-source differential amplifier; the first-stage current amplifier adopts a current mirror structure, the second-stage common-source differential amplifier adopts a common-source differential amplifier with a common-mode feedback network, the output voltage of the first-stage current amplifier is used as the input voltage of the second-stage common-source differential amplifier, and the output voltage of the second-stage common-source differential amplifier is used as the output voltage of the fully differential amplifier.

3. The ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz according to claim 2, characterized in that: The first-stage current amplifier includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; The source of the first MOS tube M1 is connected to VDD, the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1, the drain of the first MOS tube M1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the drain of the sixth MOS tube M6, the source of the sixth MOS tube M6 is grounded, the gate of the sixth MOS tube M6 is connected to the gate of the fifth MOS tube M5, the source of the fifth MOS tube M5 is grounded, the gate of the fifth MOS tube M5 is connected to the drain, the drain of the fifth MOS tube M5 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to VDD; the gate of the third MOS tube M3 is connected to Vin+, the source of the third MOS tube M3 is connected to VDD, the drain of the third MOS tube M3 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded; the gate of the fourth MOS tube M4 is connected to Vin-, the source of the fourth MOS tube M4 is connected to VDD, the drain of the fourth MOS tube M4 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is grounded.

4. The ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz according to claim 3, characterized in that: The second-stage common-source differential amplifier includes: a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8; The gate of the seventh MOS tube M7 is connected to the gate of the eighth MOS tube M8, the source of the seventh MOS tube M7 is connected to VDD, the drain of the seventh MOS tube M7 is connected to the drain of the ninth MOS tube M9, the gate of the ninth MOS tube M9 is connected to the first end of the fourth resistor R4, the source of the ninth MOS tube M9 is connected to the drain of the eleventh MOS tube M11, the source of the eleventh MOS tube M11 is grounded, and the gate of the eleventh MOS tube M11 is connected to the bias voltage VB; the source of the eighth MOS tube M8 is connected to VDD, the drain of the eighth MOS tube M8 is connected to the drain of the tenth MOS tube M10, the source of the tenth MOS tube M10 is connected to the drain of the twelfth MOS tube M12, the gate of the tenth MOS tube M10 is connected to the first end of the fifth resistor, the source of the twelfth MOS tube M12 is grounded, and the gate of the twelfth MOS tube M12 is connected to the bias voltage VB; The drain of the seventh MOS tube M7 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the source of the seventh MOS tube M7; the drain of the eighth MOS tube M8 is connected to the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is connected to the source of the eighth MOD tube M8; the first end of the eighth resistor R8 is connected to the source of the ninth MOS tube, and the second end of the eighth resistor R8 is connected to the source of the tenth MOS tube; the first end of the first capacitor C1 is connected to the source of the ninth MOS tube, and the second end of the first capacitor C1 is connected to the source of the tenth MOS tube; The gate and drain of the thirteenth MOS tube M13 are connected, and the gates of the thirteenth MOS tube M13, the fourteenth MOS tube M14, the seventh MOS tube M7 and the eighth MOS tube M8 are all connected to the feedback bias voltage VC; the source of the thirteenth MOS tube M13 is connected to VDD, the drain of the thirteenth MOS tube M13 is connected to the drain of the fifteenth MOS tube M15, the gate of the fifteenth MOS tube M15 is connected to the gate of the ninth MOS tube M9, the source of the fifteenth MOS tube M15 is connected to the drain of the nineteenth MOS tube M19, the source of the nineteenth MOS tube M19 is grounded, and the gate of the nineteenth MOS tube M19 is connected to the bias voltage VB; the source of the fourteenth MOS tube M14 is connected to VDD, the fourteenth MOS tube The drain of M14 is connected to the drain of the seventeenth MOS tube M17, the source of the seventeenth MOS tube M17 is connected to the drain of the twentieth MOS tube M20, the source of the twentieth MOS tube M20 is grounded, and the gate of the twentieth MOS tube M20 is connected to the bias voltage VB; the gate of the seventeenth MOS tube M17 is connected to the gate of the sixteenth MOS tube M16, the drain of the sixteenth MOS tube M16 is connected to the drain of the seventeenth MOS tube M17, and the source of the sixteenth MOS tube M16 is connected to the source of the fifteenth MOS tube M15; the source of the seventeenth MOS tube M17 is connected to the source of the eighteenth MOS tube M18, the drain of the eighteenth MOS tube M18 is connected to the drain of the fifteenth MOS tube M15, and the gate of the eighteenth MOS tube M18 is connected to the gate of the tenth MOS tube M10; The gate of the seventeenth MOS tube M17 and the gate of the sixteenth MOS tube M16 are connected to the expected value of the external output common mode level; The gate detection voltage of the fifteenth MOS tube M15 and the gate detection voltage of the eighteenth MOS tube M18 are used as the differential voltage outputted by the fully differential amplifier.

5. The ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz according to claim 4, characterized in that: The circuit structure of the orthogonal signal generator is a type II four-stage RC polyphase filter network.

6. The ultra-wideband silicon-based phase shifter chip operating at 0.2-2 GHz according to claim 5, characterized in that: The vector synthesis network uses an analog multiplier module architecture with two Gilbert cells sharing the same load.

Images