The invention provides a constant-ratio timing circuit for
trailing edge timing. The circuit comprises a first
resistor, a second
resistor, a
capacitor and a
comparator. One end of the second resistoris connected with a direct-current power supply, and the other end of the second
resistor is connected with one end of the first resistor and the first input end of the
comparator and then grounded through the
capacitor. A second input end of the
comparator is connected with the other end of the first resistor and an input
signal of the constant-ratio timing circuit. An output end of the comparator serves as an output end of the constant-ratio timing circuit. The direct-current power supply and the input
signal have the same direct-current component. According to the invention, only the pulsesignal is attenuated, and the
direct current component remains unchanged, so that the stability of the circuit is improved compared with the attenuation of the
direct current component and the pulsesignal in the traditional constant-ratio timing circuit. In addition, the attenuation and the time
delay are achieved only through one RC network. Compared with a traditional constant-ratio timing circuit in which quantity signals are divided into two paths to be attenuated and delayed respectively, the structure is simpler.