Timing controller for dead-time control

Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices (T1, T2) using only low voltage transistors (inside 410) are described. The apparatus (410) and methodare adapted to control multiple high voltage semiconductor devices (T1, T2) to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC / DC) and other applications wherein a first voltage (Vin) is large compared to the maximum voltage handling of the low voltage control transistors (Vdd1, Vdd2). According to an aspect, timing control of edges (fig. 4: 215, fig.14a: 1410 ) of a control signal (IN) to the high voltage semiconductor devices (T1, T2) is provided by a basic edge delay circuit (fig. 4: inside 215, fig. 14a: 1410) that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and / or an output of the basic edge delay circuit to allow for timing control of a rising edge ora falling edge of the control signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Patent Application 15 / 627,196, filed June 19, 2017, entitled "DC-Coupled High-Voltage LevelShifter," the entire disclosure of which is incorporated herein by reference. [0003] This application may be related to US Patent No. 9,484,897, issued November 1, 2016, entitled "Level Shifter," the entire disclosure of which is incorporated herein by reference. This application may be related to US Patent No. 5,416,043, issued May 6, 1995, entitled "Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer," the entire disclosure of which is incorporated herein by reference. This application may also be related to US Patent No. 5,600,169, issued February 4, 1997, entitled "Minimum charge FET fabricated on an ultrathin siliconon sapphire wafer," the entire disclosure of which is incorporated herein by reference. This application may also be related to US Patent Application Seri...

AI Technical Summary

Problems solved by technology

Since these control transistors typically have a poor FOM compared to the figure of merit (FOM) of the GaN device, which may, for example, limit the operating frequency of the GaN device, the overall circuit (e.g., power management) may be dominated by large high voltages in performance Transistors - which may be difficult to charge and discharge quickly (eg their FOM is too high) - are limited and thus the benefit of using GaN devices may be significantly reduced

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