Method for forming dual mosaic structure

Abstract

The invention discloses a method for forming a dual mosaic structure, which comprises the following steps of: providing a substrate of which the surface is provided with a conductive structure; forming a first dielectric layer on the substrate; forming a through-hole pattern on the first dielectric layer; carrying out first etching by taking the through-hole pattern as a mask; covering a second dielectric layer on the substrate with a through-hole opening; carrying out second etching on the second dielectric layer; covering a third dielectric layer on the substrate after the second etching; forming a groove pattern on the third dielectric layer; carrying out third etching by taking the groove pattern as the mask to form a groove; removing the residual second dielectric layer and the third dielectric layer on the substrate after forming the groove; and filling a metal in the through-hole opening and the groove to form the dual mosaic structure. The method for forming the dual mosaic structure can solve the problems of slopes and bulges in the dual mosaic structure formed by using the conventional method, and improves the forming quality of the dual mosaic structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a double damascene structure. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits (ULSI), the internal circuit density is getting larger and larger, and the number of components contained is increasing, making the surface of the wafer unable to provide enough area to make the required interconnection ( Interconnect). Therefore, in order to meet the increased demand for interconnection lines after component shrinkage, the design of multilayer metal interconnection lines with more than two layers has become a method that must be adopted in VLSI technology. Among them, after entering the 0.18 micron process technology, the dual damascene structure of copper and low dielectric constant (low k value, low dielectric constant) dielectric layer is often used, which can redu...

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Problems solved by technology

[0012] Due to the existence of abnormal conditions such as the slope 111 and the protrusion 112 shown in the figure, the formation quality of the barrier layer TaN formed in the dual damascene opening before filling the metal is poor, for example, it will be formed at the sidewall of the slope 111. Thinner, resulting in poor isolation effect between the filled metal and the sidewall, and finally makes the contact resistance value of the formed dual damascene structure larger

[0013] The Chinese patent application with the publication number CN1545726 published on November 10, 2004 discloses a method for forming a copper through hole, which enhances the adhesion between the through hole and the copper layer by changing the structure of the adhesion layer located in the through hole. Adhesion, to solve its open circuit problem after heat treatment

However, this method cannot effectively solve the above-mentioned problem of poor quality of the dual damascene structure caused by the deformation of the dual damascene opening.

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