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109results about How to "Reduce process difficulty" patented technology

Subcritical liquid extraction device and subcritical liquid extraction method of active ingredients of natural products

The invention provides a subcritical liquid extraction device and a subcritical liquid extraction method of active ingredients of natural products, relating to a device and a method for extracting active ingredients of natural products. The device comprises a control system part and a leaching system part, wherein the leaching system part comprises an extraction tank 1, an evaporating tank 2, a buffer tank 3, a condenser 4, a solvent tank 5, an ultrasound generating device 11, a vacuum pump 9, a fire arrester 10, a compressor 8, a hot water pump 7 and a hot water box 6; the control system partcomprises a leaching temperature controller, a leaching time controller, a leaching frequency controller, a material dissolving ratio controller, an exsolution temperature regulation controller, an exsolution pressure feedback controller, an electric appliance controller of the device and an excess-temperature excess-pressure leaking alarm. The method can select different subcritical extraction media according to different extraction products, combines a subcritical liquid extraction technology and an ultrasonic extraction technology to increase extraction rate and reduce extraction time andis a new high-efficiency low-consumption environment-friendly technology for extracting active ingredients of natural products.
Owner:HENAN YALINJIE BIOLOGICAL TECH

Semitransparent fluorescent powder/glass composite luminescent ceramic wafer and preparation method thereof

The invention relates to a semitransparent fluorescent powder/glass composite luminescent ceramic wafer and a preparation method thereof. The semitransparent fluorescent powder/glass composite luminescent ceramic wafer is obtained by carrying out 'pelletizing, compression moulding and sintering' on fluorescent powder and low-melting-point glass powder, wherein content of the fluorescent powder is 30-85wt%, and the content of the low-melting-point glass powder is 70-15wt%. The preparation method of the semitransparent fluorescent powder/glass composite luminescent ceramic wafer comprises the following steps: firstly, uniformly mixing fluorescent powder with glass powder in certain proportion, and adding a binding agent required by pelletizing and demoulding, so that pelletized powder of 60-100 meshes is obtained; secondly, carrying out compression moulding on the obtained pelletized powder by virtue of a mould, so that a green body of a certain shape is obtained; thirdly, carrying out heat treatment, namely carrying out glue drainage on the green body for 2-4 hours at the temperature of 300-395 DEG C, and sintering for 1-2 hours at the temperature of 395-410 DEG C, wherein the whole heat treatment process is carried out in the air atmosphere; and finally the fluorescent powder/glass composite luminescent ceramic wafer is obtained.
Owner:厦门百嘉祥微晶材料科技股份有限公司

Processing method of differential type high-precision accelerometer

The invention discloses a processing method of a differential type high-precision accelerometer. The accelerometer comprises an upper electrode cover plate, a movable silicon structural assembly with a beam-mass block structure and a lower electrode cover plate which are sequentially connected from top to bottom. The method comprises the following steps of: processing the upper electrode plate and the lower electrode plate by using a glass sheet or a monocrystalline silicon wafer as a substrate; processing the movable silicon structural assembly with the beam-mass block structure by using a double-device-layer SOI (Silicon-On-Insulator) monocrystalline silicon wafer as a substrate; and connecting the upper electrode plate and the lower electrode plate which are processed by using the substrates with the movable silicon structural assembly based on a bonding mode. In the invention, only one monocrystalline silicon wafer is adopted to process the movable silicon structural assembly, thereby avoiding the condition that a frequently used high-temperature silicon-silicon bonding process is used for preparing the movable silicon structural assembly, reducing the process difficulty, lowering the highest process temperature and eliminating bonding stress problems introduced by silicon-silicon bonding; and moreover, the beam-mass block structure has generality.
Owner:PEKING UNIV

Optical fiber Bragg grating pressure sensor and corresponding measurement method thereof

The invention discloses an optical fiber Bragg grating pressure sensor and a corresponding measurement method thereof, and the sensor comprises a housing, an elastic diaphragm, an L-shaped uniform strength beam and an optical fiber Bragg grating, wherein an opening is arranged at the top end of the housing, the opening and internal space of the housing constitute a cavity body, the elastic diaphragm covers the opening, the uniform strength beam is arranged in the cavity body, a pressure block is arranged at the free end of a beam arm of the uniform strength beam, a hard boss which is tightly connected with the pressure block is arranged on the lower surface of the elastic diaphragm, the optical fiber Bragg grating is mainly constituted by connecting two Bragg gratings with the identical temperature gradient in series through an optical fiber, and the two Bragg gratings are respectively connected on the upper surface and the lower surface of the beam arm. The sensor has the advantages that the elastic diaphragm is in rigid connection with the beam arm during the design, thereby not only improving the measurement precision, but also reducing the process difficulty; as the optical fiber Bragg grating is mainly constituted by the two Bragg gratings with the identical temperature gradient, the sensor can solve the temperature cross sensitivity problem during the measurement.
Owner:NINGBO SHANGONG CENT OF STRUCTURAL MONITORING &CONTROL ENG

High-frequency combustion instability coverall process simulation test automatic regulating system and method

The invention relates to high-frequency combustion instability coverall process simulation test automatic regulating system and method. The system comprises a control system, a combustor, a heat exchanger, an alcohol vaporizer and a combustion chamber, wherein the control system is used for regulating working conditions in the combustion chamber by a parameter input and flow regulating valve; the combustion chamber is an engine head with real size, an oxidant inlet and a fuel inlet of the combustion chamber are respectively communicated with the heat exchanger and the alcohol vaporizer, the oxidant inlet of the combustion chamber is provided with a sound velocity pore plate, a pressure measuring point and a temperature measuring point; the fuel inlet of the combustion chamber is provided with a sound velocity pore plate, a pressure measuring point and a temperature measuring point; and a cold air inlet of the heat exchanger is provided with a cold air flow regulating valve, and a heatsource of the heat exchanger is a combustor. The invention solves the technical problems of high cost, long period and poor safety property caused by adopting a real engine and a real working condition in the traditional simulation test, is very low in test cost, and lowers economic and labor costs.
Owner:NO 11 INST OF NO 6 ACADEMY OF CHINA AEROSPACE SCI & TECH

Pixel structure and organic light emitting display adopting same

The invention discloses a pixel structure and an organic light emitting display adopting the same. The pixel structure comprises a plurality of pixel units, wherein each pixel unit takes a rhombus structure formed by an upper half part and a lower half part; the adjacent pixel units are arranged in a staggered manner; each pixel unit comprises a plurality of sub pixels; a first sub pixel forms one of the upper half part and the lower half part of the rhombus pixel unit; a second sub pixel and a third sub pixel are arranged side by side to form the other of the upper half part and the lower half part of the rhombus pixel unit together; pixels in the same color of the pixel units in the adjacent rows are arranged adjacently. By integrating the same sub pixels together, the width of the corresponding vapor deposition Mask hole diameter can be enlarged, the difficulty of the Mask technology can be reduced, and the display PPI (Pixel Per Inch) can be improved; meanwhile, because of the staggered arrangement manner of the pixel units in the adjacent rows, the adjacent edges of the second sub pixel and the third sub pixel with the first sub pixel can be longer, main light emitting of the pixel units can be relatively concentrated, and the light mixing effect is good.
Owner:KUNSHAN GO VISIONOX OPTO ELECTRONICS CO LTD

Organic light-emitting display panel and organic light-emitting display device

The invention discloses an organic light-emitting display panel and an organic light-emitting display device. The organic light-emitting display panel comprises a substrate, a cathode layer, an anode layer, a plurality of metal layers and an insulating medium, wherein the anode layer is located between the substrate and the cathode layer; the plurality of metal layers are located between the substrate and the anode layer; the insulating medium is located between the metal layers and the cathode layer; the anode layer comprises an anode region; the cathode layer is multiplexed as a first pressure-sensitive electrode; a second pressure-sensitive electrode is arranged on the metal layer or in a region not overlapping with the anode region of the anode layer; and the first pressure-sensitive electrode, the second pressure-sensitive electrode and the insulating medium located between the first pressure-sensitive electrode and the second pressure-sensitive electrode are used for sensing pressure. The organic light-emitting display panel and the organic light-emitting display device can achieve pressure sensing on the basis of an existing organic light-emitting display panel; the manufacturing cost is reduced; and the thickness of a pressure-sensitive display device is reduced.
Owner:SHANGHAI TIANMA MICRO ELECTRONICS CO LTD +1

Semiconductor structure and manufacturing method thereof

The invention provides a semiconductor structure manufacturing method, which is applied to the technical field of manufacturing of capacitor contact nodes of memories. The method at least comprises the following steps of: forming a plurality of bit line structures on a substrate; forming a plurality of dielectric walls on the substrate, wherein the upper surfaces of the dielectric walls are higherthan the upper surfaces of the bit line structures, and the dielectric walls extend to cover the parts, overlapped with the bit line structures, of the dielectric walls; manufacturing an insulating structure in a capacitor storage node window defined by the bit line structures and the dielectric walls to form a separated capacitor storage node window; depositing a conductive material layer in theseparated capacitor storage node window; and etching back the conductive material layer, and forming capacitor contact node structures on the two sides of the insulating structure. The invention alsoprovides a semiconductor structure. By applying the embodiment of the invention, the manufacturing yield of the capacitor contact node structures is improved, so that the problem that the conductivecharacteristic of a circuit is influenced because etched patterns are easy to deviate due to the fact that a thicker polycrystalline silicon layer between storage nodes is etched in the prior art is avoided.
Owner:CHANGXIN MEMORY TECH INC

Manufacturing method for cavity of full silica-based microfluidic device

The invention provides a manufacturing method for a cavity of a full silica-based microfluidic device, comprising the following steps of: providing (111) a crystal-oriented single crystal silicon substrate, on which an oxide layer is formed; patterning the oxide layer, and exposing a plurality of square window patterns; taking the oxide layer as a mask to etch the silicon substrate so as to form an upper-layer deep groove; depositing protection layers on the surface of the oxide layer and on the sidewalls and the bottom of the upper-layer deep groove; removing the protection layer on the surface of the oxide layer and the protection layer on the bottom of the upper-layer deep groove; taking the protection layers on the oxide layer and the protection layer on the sidewalls of the upper-layer deep groove as masks to etch the silicon substrate so as to form a lower-layer deep groove; etching the lower-layer deep groove through a wet etching method, and forming the cavity in the silicon substrate; fully filling holes of the upper-layer deep groove, and sealing off the cavity; and taking the oxide layer as the mask to etch the silicon substrate so as to form four reaction tanks communicated with the cavity. In the manufacturing method provided by the invention, machining is executed based on a single silicon substrate in the cavity forming process, by a mode of firstly forming a bottom cavity in a layering manner and then filling the deep groove, the cavity can be formed without being related to a silica bonding or gluing technology.
Owner:ADVANCED SEMICON MFG CO LTD

Sewing method of double-embedded-wire pocket

The invention provides a sewing method of a double-embedded-wire pocket. A pocket center line is drawn in the front side pocket position part of a clothes piece and is used as a positioning line; the rough edge on the top of wire-embedded cloth is downwards flanged for a first distance, the flanged part is subjected to buckling ironing for forming a first flanging line, then, the edge is downwards flanged for a second distance being the twice length of the first distance, and the part which is flanged again is subjected to buckling ironing for forming a second edge flanging line; in the second step, the rough edge, downwards flanged for the first distance, of the wire-embedded cloth is aligned with the center line of the pocket, a press foot with the same width as the first distance is adopted for sewing a first embedded wire in the middle position of the flanged edge with the same width as the first distance, and during the sewing, the lower edge of the press foot is aligned with the positioning line; the press foot is adopted for sewing a second embedded wire in the middle position between the rough edge of the wire-embedded cloth and the second edge flanging line, during the sewing, the press foot is just pressed on a fabric with the same width as the first distance between the rough edge and the second edge flanging line, and the two sides of the press foot are respectively aligned with the rough edge and the second edge flanging line.
Owner:JIANGXI INST OF FASHION TECH

Semiconductor structure and manufacturing method thereof

The invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the steps of: providing a substrate comprising a first region and a second region; forming an interlayer dielectric layer on the substrate; forming a first opening through which the substrate is exposed in the interlayer dielectric layer in the first region, and forming a second opening through which the substrate is exposed in the interlayer dielectric layer in the second region; forming gate dielectric layers on the bottom part and the side wall of the first opening as well as that of the second opening; forming a second work function layer on the gate dielectric layer in the second region; converting a partial thickness of the second work function layer into a barrier layer; forming a first work function layer on the gate dielectric layer in the first region and the barrier layer in the second region; and forming a metal layer which fills up the first opening and the second opening. According to the semiconductor structure and the manufacturing method thereof, the partial thickness of the second work function layer is converted into the barrier layer, the barrier layer can prevent metal ions in the first work function layer from diffusing into the second work function layer, and an additional film layer is not introduced, thereby avoiding adverse influence on the performance of the second work function layer.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

MEMS wafer level vacuum packaging structure and method

The invention discloses an MEMS wafer level vacuum packaging structure and method. The packaging structure comprises an insulation substrate, an MEMS chip structural layer and a cover plate, and the above components are connected through a wafer level bonding mode to form a vacuum cavity. The center of a first bonding ring is provided with a second bonding ring which is not totally closed, two types of bonding modes can be achieved in the same technical condition, because the bonding temperatures of anode bonding, gold and silicon eutectic bonding, hot pressing bonding or adhesion bonding are similar, so a vacuum packaging structure and metal wires can be transversally connected. In addition, the designed second bonding ring is slightly higher than the first bonding ring to make two bonding ring fully contact with each other during bonding, the second bonding ring is not totally closed, so on the one hand, metal wires can be transversally connected, and on the other hand, the vacuum cavity can be separated from the external environment, to make sure that the vacuum cavity is sealed. The MEMS wafer level vacuum packaging structure and method are simple in technology, the reliability and yield of device can be raised, and the application of MEMS wafer level vacuum packaging technology in a large scale scope can be promoted.
Owner:CHONGQING UNIV

Marine environment information subsurface buoy device based on multi-parameter sensor

ActiveCN111071390AConvenient post-maintenance and repairReduce process difficultyWaterborne vesselsBuoysSeawaterVertical array
The invention discloses a marine environment information subsurface buoy device based on a multi-parameter sensor. The marine environment information subsurface buoy device mainly comprises a pressure-resistant floating ball, a measuring vertical array, a subsurface buoy system and an anchoring system which are sequentially connected from top to bottom. The measuring vertical array is formed by movably connecting a plurality of sub-sections for acquiring environmental information; a subsurface buoy module is arranged in the subsurface buoy system and used for synchronously storing and measuring data information output by the last subsection of the vertical array. The beneficial effects of the marine environment information subsurface buoy device are as follows: the requirements of design specifications for observing hydrological environment and marine environment noise in medium and shallow sea areas are met; and the device has the capabilities of marine environmental noise measurement, underwater acoustic signal measurement, seawater temperature measurement and seawater pressure measurement. An effective way is provided for measuring the hydrological environment and the marine environment noise level of the marine survey and measurement ship in the medium-shallow sea area, the marine environment noise measurement capacity, the underwater acoustic signal measurement capacity, the seawater temperature measurement capacity and the seawater pressure measurement capacity are enhanced, and the domestication technical level of applying marine instruments is improved.
Owner:THE 715TH RES INST OF CHINA SHIPBUILDING IND CORP

Method for manufacturing integrated circuit

The invention provides a method for manufacturing an integrated circuit and relates to the field of integrated circuit manufacture. The method can reduce the process difficulty and improve the flexibility of integrated circuit process development and integrated circuit design. The method for manufacturing an integrated circuit comprises the following steps: forming an N well and a P well on a substrate; sequentially forming a field oxide layer, a first polycrystalline silicon layer pattern and an insulating medium layer pattern respectively on field regions of the N well and the P well, wherein the first polycrystalline silicon layer pattern includes a lower electrode plate of a double polycrystalline silicon capacitor located on the field oxide layer, and a first polycrystalline silicon layer resistor; forming a gate oxide layer on active regions of the N well and the P well; forming a second polycrystalline silicon layer pattern on the gate oxide layer, the field oxide layer and the insulating medium layer pattern, wherein the second polycrystalline silicon layer pattern includes a polycrystalline silicon gate located on the gate oxide layer, a second polycrystalline silicon layer low-value resistor located on the field oxide layer, and an upper electrode plate of the double polycrystalline silicon capacitor located on the insulating medium layer; and forming a source and drain regions in the active regions.
Owner:FOUNDER MICROELECTRONICS INT
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