Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure manufacturing method, which is applied to the technical field of manufacturing of capacitor contact nodes of memories. The method at least comprises the following steps of: forming a plurality of bit line structures on a substrate; forming a plurality of dielectric walls on the substrate, wherein the upper surfaces of the dielectric walls are higherthan the upper surfaces of the bit line structures, and the dielectric walls extend to cover the parts, overlapped with the bit line structures, of the dielectric walls; manufacturing an insulating structure in a capacitor storage node window defined by the bit line structures and the dielectric walls to form a separated capacitor storage node window; depositing a conductive material layer in theseparated capacitor storage node window; and etching back the conductive material layer, and forming capacitor contact node structures on the two sides of the insulating structure. The invention alsoprovides a semiconductor structure. By applying the embodiment of the invention, the manufacturing yield of the capacitor contact node structures is improved, so that the problem that the conductivecharacteristic of a circuit is influenced because etched patterns are easy to deviate due to the fact that a thicker polycrystalline silicon layer between storage nodes is etched in the prior art is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor memory, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] Dynamic random access memory (DRAM) is a widely used semiconductor product, and its basic storage unit includes an access transistor and a capacitor. With the continuous reduction of the semiconductor feature size, the area of ​​the capacitor contact node is getting smaller and smaller, and the manufacturing difficulty is getting more and more difficult. The alignment deviation of the photolithography process and the increase in the difficulty of the etching process seriously affect the electrical reliability of the memory capacitor contact node, resulting in an open circuit of the capacitor contact electrode or a short circuit with an adjacent contact electrode, reducing the yield of the memory chip. Contents of the invention [0003] In view of the above-mentioned shortco...

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Problems solved by technology

[0003] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and its man

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