109 results about "Eutectic bonding" patented technology

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

The invention discloses a vertical-structure LED chip and a manufacturing method thereof, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps of epitaxial growth, first-round photoetching processing, eutectic bonding, substrate stripping, second-round photoetching processing and chip segmentation. Wherein a pretreatment structure is obtained after the substrate is stripped, and the N-GaN layer is exposed on the surface of the pretreatment structure; the second round of photoetching processing comprises the following steps: etching the exposed N-GaN layer to form an N hole protection structure; and carrying out roughening treatment on the surface of the N-GaN layer on which the N hole protection structure is formed. According to the invention, the N hole protection structure is formed on the N-GaN layer, so that the hole channel formed by processing the P-GaN surface can be effectively protected, and the electric leakage risk of the LED chip with the vertical structure can be reduced.

The invention relates to the technical field of semiconductor packaging, in particular to a film expanding mechanism and a memory bank main control chip die bonder. The memory bank main control chip die bonder comprises an operation machine table, an eutectic system, a first feeding system, a second feeding system and a visual positioning system, and the eutectic system comprises a die bonding bearing table, a two-dimensional motion module connected to the lower portion of the die bonding bearing table and a dispensing mechanism arranged above the die bonding bearing table. The die bonding device comprises a die bonding bearing table and a die bonding heating assembly arranged on the die bonding bearing table, the die bonding bearing table is provided with a plate channel, the die bonding heating assembly comprises a material carrying top plate and a heating piece arranged in the material carrying top plate, and the material carrying top plate is located in the plate channel; the first feeding system comprises a chip feeding table, a two-dimensional moving module and a wafer taking device, the two-dimensional moving module is used for driving the chip feeding table to move, and the wafer taking device comprises an ejector pin mechanism and a chip conveying mechanism. According to the invention, the eutectic die bonding function and the adhesive die bonding function are integrated on one device at the same time.

The invention relates to the technical field of optical devices, and particularly discloses a preparation method of an electrostatic drive MEMS Fabry-Perot filter, an SOI wafer is used as a first substrate, top silicon of the SOI wafer is used as a drive structure of the MEMS Fabry-Perot filter, the thickness and mechanical characteristics of a cantilever can be accurately adjusted, and the MEMS Fabry-Perot filter can be manufactured. And meanwhile, the silicon dioxide insulating layer of the SOI wafer can also be used as an etching stopping layer, so that the condition of excessive etching is avoided, and the manufacturing yield of the filter is further improved. When the bonding layer and the silicon dioxide insulating layer of the SOI wafer are etched, an etching method combining advanced oxide etching and reactive ion etching is adopted, isotropy and anisotropy are integrated, and the limitation of a single process is overcome. A certain dislocation amount of linear offset is reserved during patterning of bonding metal, gold-tin eutectic bonding is adopted, the problem of leading-out of top and bottom electrodes is solved, and the machining cost and uncertainty are reduced.

Eyeglasses may include left and right adjustable lenses. Each adjustable lens may include a stack of liquid crystal cells that are interconnected using vertical interconnect structures such as through-substrate-vias, conductive beads in a liquid crystal sealant, anisotropic conductive adhesive, conductive epoxy, diffusion bonds, eutectic bonds, and / or other suitable interconnect structures. Each liquid crystal cell in the stack may include liquid crystal material sandwiched between first and second substrates. A sealant may surround the liquid crystal material and may include conductive beads that form intra-cell connections between the first and second substrates of that liquid crystal cell. Through-substrate-vias may be formed in the substrate and may be coupled to the conductive beads in the sealant. Anisotropic adhesive, conductive epoxy, or other conductive material may be located between the liquid crystal cells and may be used to form inter-cell connections in the stack.

The invention provides a three-wafer bonding MEMS device and a preparation method thereof, the three-wafer bonding MEMS device comprises a first wafer, a second wafer, a third wafer, an insulating layer and a metal electrode, the first wafer comprises a plurality of first grooves, the bottom of each first groove is communicated with at least one silicon groove, and each silicon groove is filled with an insulating material; protruding silicon-silicon bonding platforms are arranged between the first grooves and inside the first grooves. The second wafer is connected with the first wafer through a silicon-silicon bonding platform, and a plurality of strip holes are formed in the second wafer; the third wafer comprises a plurality of second grooves; a limiting bulge can be arranged in the second groove; a raised eutectic bonding platform is arranged between the interior of the second groove and the second groove, and the third wafer is bonded with the second wafer; the insulating layer covers the first wafer; the plurality of metal electrodes are disposed on the insulating layer. According to the invention, the problem that the electrical parameters of the silicon-silicon bonding process cannot be tested and represented in the production and manufacturing of the MEMS device is solved.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic / solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic / solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

The present disclosure provides a method for preparing a solar cell, a solar cell, and a solar cell module. An example solar cell includes a solar cell body, a first conductive pattern and a second conductive pattern sequentially laminated on the solar cell body, and electrically connected through one of welding, eutectic bonding, a conductive adhesive pattern between the first and the second conductive patterns, or a third conductive pattern between the first and the second conductive patterns. The conductive adhesive pattern comprises a conductive material and an adhesive. The third conductive pattern includes a first part close to the first conductive pattern, a second part close to the second conductive pattern, and a middle part between the first and the second parts. A grain size of the third conductive pattern increases from the first part to the middle part and increases from the second part to the middle part.

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

The invention discloses a semiconductor device with a gas guide groove structure and a preparation method thereof, and belongs to the technical field of semiconductor devices and processing technologies thereof. The method comprises the following steps of: depositing a first metal layer on the surface of a silicon-based CMOS (Complementary Metal Oxide Semiconductor) with a reserved cutting channel, evaporating an ITO (Indium Tin Oxide) film on the surface of a GaN epitaxial wafer of a sapphire / silicon substrate, performing annealing treatment, depositing a second metal layer, and etching by utilizing an IBE (Indium Boron Emission) process or a metal stripping process to obtain a latticed gas guide groove structure; performing ultrasonic eutectic bonding after the air guide groove is aligned with the reserved cutting channel, and finally cutting through the substrate, the N-GaN layer and the quantum well layer on the back surface of the substrate along the air guide groove structure, so that the air guide groove is communicated with air; and then the sapphire substrate is peeled off through laser or the silicon substrate is ground off, and then the N-GaN layer is thinned, so that the semiconductor device with the gas guide groove structure is prepared. According to the method, high-precision bonding equipment does not need to be used, so that the equipment investment is reduced, and a good technical effect is achieved.

A method of manufacturing a semiconductor element unit, including: joining a semiconductor element to an electrode of a first substrate, the first substrate having a first sacrificial layer and the electrode formed on the first sacrificial layer; causing eutectic bonding between the semiconductor element and the electrode by an annealing process, after the semiconductor element is joined to the electrode, to form a semiconductor element unit; and separating the semiconductor element unit by removing the first sacrificial layer after the semiconductor element and the electrode are connected by eutectic bonding.

The invention provides a bonding structure, an MEMS device and a bonding method, and the bonding structure comprises a first wafer, the surface of the first wafer is provided with a projection, and the surface of the projection is provided with a plurality of first bonding metal layers which are arranged at intervals; a plurality of second bonding metal layers which are arranged at intervals are arranged at positions, corresponding to the bulges, on the surface of the second wafer; the second wafer and the first wafer form a bonding structure through eutectic bonding between the first bonding metal layer and the second bonding metal layer; wherein the orthographic projection of the first bonding metal layer on the bulge and the orthographic projection of the second bonding metal layer on the bulge are at least partially not overlapped. According to the embodiment of the invention, the orthographic projection of the first bonding metal layer on the projection and the orthographic projection of the second bonding metal layer on the projection at least partially do not coincide, the non-coincident position forms a complementary structure during bonding to store overflow, the overflow risk is reduced, the coincident position forms a bonding structure through eutectic melting, and the bonding strength is ensured.

The invention provides an LED chip with an electrostatic protection function and a preparation method thereof, and the method comprises the following steps: growing an epitaxial layer on a substrate, the epitaxial layer comprising an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked from bottom to top; etching a through hole in the epitaxial layer to expose the N-type semiconductor layer; preparing a dielectric layer, a reflecting layer, a wafer bonding barrier layer and a wafer bonding bonding layer, and carrying out eutectic bonding on the wafer bonding bonding layer and the wafer bonding bonding layer on the substrate; removing the substrate; performing Schottky electrode protection photoetching; preparing an edge removing layer, and photoetching the epitaxial layer to form a channel; preparing a passivation layer, and preparing a Schottky electrode; and patterning the passivation layer and the edge removing layer to prepare an N-surface electrode. According to the invention, the Schottky diode is arranged below the bonding pad of the LED chip, so that the anti-electrostatic discharge capability of the LED is improved on the premise that the optical power is not sacrificed.

The invention belongs to the technical field of intelligent power modules, and discloses an intelligent power module and a manufacturing method thereof.The intelligent power module comprises a substrate, a chip function layer, a function module assembly and a plurality of intelligent power module pins, and the function module assembly comprises a metal substrate plate, a plurality of function components and a plurality of function module pins; and the functional module assembly is mounted on the chip functional layer through the mounting surface of the metal substrate plate. According to the intelligent power module, through the hierarchical integrated design of the function module assembly and the chip function layer, compared with an existing scheme in which all function chips are discretely mounted on a substrate and depend on a complex structure of eutectic welding and DA equipment, the function module assembly is directly mounted on the chip function layer through a mounting surface in a pre-integrated form, so that the structure of the chip function layer is simplified; extra copper radiating fins and eutectic welding equipment are not needed, so that the input cost of special equipment is reduced.

This invention provides a eutectic bonding fixture and bonding method, relating to the technical field of chip processing. The eutectic bonding fixture includes a base, an assembly plate, and a cover plate. The cover plate has a through-hole for machining. The assembly plate and the cover plate are arranged from bottom to top. There are multiple assembly plates arranged sequentially along a direction perpendicular to the base. Each assembly plate is equipped with a housing positioning stage, and at least two assembly plates have housing positioning stages of different types. The assembly plate and / or the cover plate are movably connected to the base so that the downward projection of the machining hole can fall on the housing positioning stage to be worked, and the unworked housing positioning stage is located within the downward projection path of the cover plate.

The invention relates to a metal eutectic bonding MEMS pressure sensor and a preparation method thereof, and belongs to the technical field of micro electro mechanical systems. The invention provides a metal eutectic bonding MEMS pressure sensor and a preparation method thereof. The sensor comprises a base, a lower bonding film, an upper bonding film, a substrate, an insulating film, a resistor strip and a thermistor film. The substrate, the insulating film, the resistor strip and the thermistor film form a core body; the silicon substrate manufactured through the MEMS technology is used as a core body, and the problem that the MEMS technology cannot be used for a metal elastomer in a traditional sputtering film type pressure sensor is solved. Aiming at the problems of an existing MEMS pressure sensor during assembly and system integration, low-stress connection between a core body and a metal base is realized by adopting a metal eutectic bonding technology, additional stress caused by difference of thermal expansion coefficients is effectively relieved, and by utilizing the characteristics of high strength and high stability of a metal eutectic bonding structure, the MEMS pressure sensor can be assembled and integrated with a system. The technical problem that the chip is easily damaged due to stress concentration in a gluing / welding mode is solved.

This invention provides an automated eutectic bonding method and apparatus, relating to the field of microelectronic packaging technology. The method includes: heating a carrier plate placed on a eutectic platform and the eutectic solder thereon to melt the eutectic solder into molten solder; using a suction nozzle to pick up a chip; controlling the suction nozzle to carry the chip vertically, pressing it down onto the molten solder and applying a first pressure, then vertically lifting the chip to detach it from the surface of the molten solder; repeating the pressing and lifting action at least twice; after the final pressing, maintaining a second pressure and controlling the eutectic platform to cool, allowing the molten solder to solidify and complete the bonding. This invention, through multiple reciprocating pressing movements perpendicular to the bonding plane, promotes the wetting of the back side of the chip by the molten solder, achieving low-void, high-quality eutectic bonding.

The invention provides a transducer which can be reliably bonded in a bonding region and has high reliability. The transducer includes: a second semiconductor substrate on which a first insulating layer having a first metal layer provided on a surface thereof is disposed; a first semiconductor substrate which is disposed so as to overlap the second semiconductor substrate and on which a second insulating layer having a second metal layer provided on the surface thereof is disposed; a functional element provided between the first semiconductor substrate and the second semiconductor substrate; and a eutectic reaction layer that bonds the first semiconductor substrate and the second semiconductor substrate in a bonding region located around the functional element, the eutectic reaction layer being a bonding layer formed by eutectic bonding of the first metal layer and the second metal layer. At least one of the first insulating layer and the second insulating layer is provided with a recessed portion having a bottom portion wider than the width of the bonding region, and the bonding region is disposed at the bottom portion.

An electronic device comprises a target substrate, a micro semiconductor structure array, a conductor array, and a connection layer. The micro semiconductor structure array is disposed on the target substrate. The conductor array corresponds to the micro semiconductor structure array, and electrically connects the micro semiconductor structure array to a pattern circuit of the target substrate. The conductors of the conductor array are independent from one another. Each conductor is an integrated member formed by eutectic bonding a conductive pad of the target substrate and a conductive electrode of the corresponding one of the micro semiconductor structures of the micro semiconductor structure array. The connection layer connects the micro semiconductor structures to the target substrate. The connection layer excludes a conductive material. The connection layer contacts and surrounds the conductors, so that the connection layer and the conductors together form a one-layer structure.

To improve the reliability of mounting through bonding and eutectic bonding.SOLUTION: A bonding device includes: a transport mechanism for transporting a substrate; a bonding tool for bonding an electronic component to the substrate; and an anti-oxidation path extending along the transport mechanism and having a wall surrounding the transport mechanism. Therein the anti-oxidation path includes: an inlet for introducing the substrate; an opening that allows the bonding tool and the substrate to approach to or move away from each other; a gas inlet for introducing an anti-oxidation gas inside the wall; and an electrode having a passage hole through which the anti-oxidation gas passes, inside the wall, the electrode converting the anti-oxidation gas into plasma when the anti-oxidation gas passes through the passage hole.SELECTED DRAWING: Figure 1

The invention discloses a chip bonding method, a display panel and a display device, and the method comprises the steps: providing a backboard which is provided with a plurality of holes which are not conducted, and the whole layer of the backboard is coated with an adhesive solution; a light-emitting chip is transferred to the surface, provided with the bonding glue solution, of the back plate; the back plate is heated so that the multiple holes can be communicated, the adhesive liquid flows out of the multiple holes to drive the light-emitting chip to move in the direction close to the back plate, and bonding of the light-emitting chip and the back plate is achieved. The problem that the production cost of the whole display panel is high due to the fact that special equipment and process conditions are needed in a mode of pressing eutectic bonding in a high-temperature and high-pressure environment in the prior art is solved.

A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and / or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

The present invention proposes a vertical LED chip and a method for preparing the same. The method comprises: growing an undoped semiconductor layer and a second-type semiconductor layer on a sapphire substrate; depositing a transparent conductive layer on the second-type semiconductor layer, and using a laser to peel off the sapphire substrate; employing dry etching to etch from the undoped semiconductor layer to the transparent conductive layer; sequentially depositing a SiO2 layer, a reflective layer, a barrier layer, and a eutectic bonding layer on the undoped semiconductor layer; obtaining an aluminum nitride substrate, and depositing a eutectic bonding layer on the aluminum nitride substrate; and bonding the eutectic bonding layer on the SiO2 layer to the eutectic bonding layer on the aluminum nitride substrate. The method for preparing the vertical LED chip proposed in the present invention utilizes a substrate peeling process to release epitaxial lattice stress, effectively improving the internal quantum efficiency of the epitaxial layer. Furthermore, the use of an aluminum nitride substrate with excellent heat dissipation properties facilitates heat dissipation during chip operation, improving the chip's reliability under high current conditions.

This invention discloses a CPO eutectic bonding method and system for material transfer, eutectic bonding, and other processes, comprising the following steps: controlling a material movement adjustment mechanism to move to the pick-up station, picking up a chip via a pick-up head, and transferring the chip to the bonding station; preheating the chip to a first set temperature using a heating module; moving the chip above the substrate solder layer and aligning the chip with the substrate solder layer, then controlling the heating end face of the pick-up head to heat up to a second set temperature, melting the eutectic solder between the chip and the substrate; after the heating end face of the pick-up head reaches the eutectic temperature and stabilizes for a first set time, applying a set bonding pressure to evenly spread the molten solder at the interface between the chip and the substrate, and continuously maintaining the temperature and pressure for a second set time to completely melt the solder. This invention can solve the problem of low mass production efficiency and meet the needs of large-scale CPO packaging.

The application designs a resonant pressure sensor based on C-SOI and a manufacturing method. The C-SOI with high device layer thickness uniformity is manufactured by gold-silicon eutectic bonding and mechanical chemical polishing processes, and the pressure sensitive membrane and resonator aligned with the pre-embedded groove are manufactured by using the bonding wafer through photoetching and deep etching processes, and the silicon wafer and the C-SOI are bonded together by using the gold-silicon eutectic bonding process to realize the vacuum packaging of the resonator. The silicon resonant pressure sensor designed by the application can realize high-precision measurement of gas pressure, and the differential output of the double resonator can greatly improve the pressure sensitivity of the sensor, reduce the temperature drift of the sensor and reduce the static pressure error of the sensor in the measurement process. The cavity thickness of the C-SOI is accurately controlled, the influence of side drilling on the performance of the resonator is eliminated, and the resonator failure caused by the release of hydrogen fluoride is eliminated.

The invention discloses a semiconductor chip adopting a diamond heat sink and a preparation method of the semiconductor chip, and the semiconductor chip comprises a power chip which is a high-power semiconductor chip with high energy density and high heating; the heat conduction substrate is a common heat sink substrate; the diamond deposition layer is a patterned diamond film deposited on the heat conduction substrate; the transition layer is arranged on the side, away from the heat conduction substrate, of the diamond deposition layer and used for enhancing the binding force and preventing interface reaction; and the graphical metallization layer is arranged on one side, far away from the diamond deposition layer, of the transition layer and is used for realizing welding or eutectic bonding with the power chip. A high-efficiency heat conduction path is adopted, a thick metal bonding area directly located below the chip provides a low-thermal-resistance vertical heat conduction channel, and a graphical stress buffer structure ensures transverse heat conduction and avoids huge thermal stress caused by full coverage of metal at the same time.

The invention belongs to the technical field of gas detection and optical measurement, and discloses an intermediate infrared spectrometer and a detection method thereof. The mid-infrared spectrometer comprises a constant-temperature cavity and a measuring system connected with the constant-temperature cavity, wherein the constant-temperature cavity comprises a shell, a spiral flow channel formed in the shell, an annular base embedded and mounted in the spiral flow channel, and an optical fiber mounted in the annular base. The optical fiber is connected with the annular base through eutectic bonding, a through hole array is arranged on the inner wall of the annular base, a temperature-sensitive shape memory polymer is filled between the annular base and the spiral flow channel, and the optical fiber comprises a hollow base body, a metal film arranged on the inner surface of the hollow base body and a protective layer arranged on the inner surface of the metal film. The porous adsorption coating layer is arranged on the outer surface of the hollow substrate. The infrared spectrometer has the advantages of high sensitivity, high stability, strong environmental adaptability and compact structure, and can realize high-precision and reliable detection of trace gas isotopes in a complex field environment.

The application discloses an anti-vibration CPO optical coupling fixing structure and a preparation method thereof. The structure comprises a silicon base material, a three-stage buffer slope positioning groove is formed in the silicon base material, and the three-stage buffer slope positioning groove comprises a guiding area, a stress release area and a locking area in sequence. A metallization layer is arranged on the inner wall of the locking area, and an optical fiber is metallurgically combined with the metallization layer through AuSn eutectic solder. MEMS cantilever stress compensators composed of U-shaped cutting gaps and silicon island cantilevers are arranged on both sides of a fiber entry point of the positioning groove on the silicon base material. The preparation method comprises silicon base positioning groove etching, metallization treatment, optical fiber eutectic bonding and MEMS cantilever processing. Through the synergistic effect of the three-stage buffer positioning groove, eutectic solder rigid fixing and the MEMS cantilever stress compensation, the coupling loss fluctuation is less than or equal to 0.2 dB under 50G high impact, typical equipment vibration frequency bands are effectively isolated, and the alignment offset problem of the optical fiber and the photonic chip coupling interface in an extreme environment is solved.

The invention provides a wafer MEMS air pump based on a PZT piezoelectric film, and relates to the technical field of MEMS and fluid control, the wafer MEMS air pump comprises an upper plate, a middle plate and a lower plate, the top of the middle plate and the bottom of the upper plate are mutually bonded and connected based on an Au-Sn eutectic bonding part, and the middle plate and the lower plate are connected in a covalent bonding mode adopting PDMS pretreatment. The invention is suitable for various small and miniature portable equipment and other application scenes, adopts an MEMS (Micro-Electro-Mechanical System) integrated process, does not need to be assembled, and is good in process consistency and low in batch production cost; the working frequency of the core PZT piezoelectric film resonator is high (usually in an ultrasonic frequency band), ultrasonic waves generated by vibration cannot be heard, and compared with a traditional mechanical miniature air pump in a noise-pollution-free preparation mode, the miniature air pump is simple in structure, good in impact resistance and not prone to damage.