13 results about "Eutectic bonding" patented technology

This invention provides a eutectic bonding fixture and bonding method, relating to the technical field of chip processing. The eutectic bonding fixture includes a base, an assembly plate, and a cover plate. The cover plate has a through-hole for machining. The assembly plate and the cover plate are arranged from bottom to top. There are multiple assembly plates arranged sequentially along a direction perpendicular to the base. Each assembly plate is equipped with a housing positioning stage, and at least two assembly plates have housing positioning stages of different types. The assembly plate and / or the cover plate are movably connected to the base so that the downward projection of the machining hole can fall on the housing positioning stage to be worked, and the unworked housing positioning stage is located within the downward projection path of the cover plate.

This invention provides an automated eutectic bonding method and apparatus, relating to the field of microelectronic packaging technology. The method includes: heating a carrier plate placed on a eutectic platform and the eutectic solder thereon to melt the eutectic solder into molten solder; using a suction nozzle to pick up a chip; controlling the suction nozzle to carry the chip vertically, pressing it down onto the molten solder and applying a first pressure, then vertically lifting the chip to detach it from the surface of the molten solder; repeating the pressing and lifting action at least twice; after the final pressing, maintaining a second pressure and controlling the eutectic platform to cool, allowing the molten solder to solidify and complete the bonding. This invention, through multiple reciprocating pressing movements perpendicular to the bonding plane, promotes the wetting of the back side of the chip by the molten solder, achieving low-void, high-quality eutectic bonding.

This invention discloses a CPO eutectic bonding method and system for material transfer, eutectic bonding, and other processes, comprising the following steps: controlling a material movement adjustment mechanism to move to the pick-up station, picking up a chip via a pick-up head, and transferring the chip to the bonding station; preheating the chip to a first set temperature using a heating module; moving the chip above the substrate solder layer and aligning the chip with the substrate solder layer, then controlling the heating end face of the pick-up head to heat up to a second set temperature, melting the eutectic solder between the chip and the substrate; after the heating end face of the pick-up head reaches the eutectic temperature and stabilizes for a first set time, applying a set bonding pressure to evenly spread the molten solder at the interface between the chip and the substrate, and continuously maintaining the temperature and pressure for a second set time to completely melt the solder. This invention can solve the problem of low mass production efficiency and meet the needs of large-scale CPO packaging.

The application provides a CMOS-MEMS integrated pressure sensor and a preparation process thereof. The pressure sensor comprises a bonded MEMS wafer and a CMOS wafer; a bonding sealing area and a PAD vertical interconnection structure in the bonding sealing area are arranged between the MEMS wafer and the CMOS wafer; the bonding sealing structure is formed by eutectic bonding of a metallization layer and a metal solder ball formed in corresponding bonding areas of the two wafers, and the bonding sealing structure surrounds a sensitive element to form a sealed cavity; the PAD vertical interconnection structure comprises conductive bumps respectively formed on the two wafers, the two conductive bumps are aligned with each other and bonded, and electrical interconnection between the MEMS wafer and the CMOS wafer is realized. The electrical interconnection of the pressure sensor realizes monolithic integration, not only improves the problems of increased signal transmission loss, reduced detection precision caused by additional parasitic resistance, capacitance and inductance introduced by wire bonding, and external noise interference, but also improves the service life and reliability, and reduces the size of the chip.

The application discloses a silicon-based piezoresistive differential pressure pressure sensor packaging structure, a method and a limiting assembly device, relates to the technical field of pressure sensor packaging, and comprises a metal base, an adapter and a silicon-based piezoresistive pressure sensitive chip. The metal base is internally provided with a penetrating internal air channel; the adapter is made of glass, is fixed to the upper surface of the metal base through a first adhesive layer, and is internally provided with a through hole in communication with the internal air channel of the metal base; the first adhesive layer is a polymer adhesive layer with stress buffering capacity; the silicon-based piezoresistive pressure sensitive chip is fixed to the upper surface of the adapter through a eutectic bonding layer and corresponds to the position of the through hole, so that the measured pressure transmitted by the internal air channel can act on the chip. The application can simultaneously consider the mechanical stability of chip connection, ultrahigh air tightness, excellent thermal stress adaptability and long-term measurement precision stability.

This invention discloses a vertical LED chip and its fabrication method, relating to the field of semiconductor technology. The method includes forming a light-emitting structure layer and a first bonding layer on a growth substrate; the light-emitting structure layer has an N-type conductive via, and the first bonding layer forms a bonding insertion hole within the N-type conductive via; forming an auxiliary bonding layer and a second bonding layer on a conductive support substrate; the auxiliary bonding layer consists of auxiliary bonding pillars, and the second bonding layer covers the outer surface of the auxiliary bonding pillars to form a bonding plug; roughening the two bonding layers and eutectic bonding them; inserting the bonding plugs into the corresponding bonding insertion holes; peeling off the growth substrate and forming a P-electrode in the exposed light-emitting structure layer; using the conductive support substrate as the N-electrode; and cutting to obtain the vertical LED chip. This invention, through the cooperation of the bonding insertion holes and bonding plugs, and the roughening treatment of the bonding layer surface, can effectively reduce the generation of bonding voids, which is beneficial to improving the reliability of the vertical LED chip.

This application discloses a high-precision eutectic bonding equipment for semiconductors, including a feeding assembly comprising a feeding platform on which semiconductor material is placed; a eutectic heating assembly comprising a eutectic heating stage for eutectic bonding of the semiconductor material; a bonding head assembly comprising a ZR bonding head, a height sensor, and a head vision system, wherein the ZR bonding head is used for transferring the semiconductor material between the feeding platform and the heating stage, and the height sensor is used to measure the height between the ZR bonding head and the feeding platform and the eutectic heating stage; a calibration assembly comprising an origin calibration sensor and a force control sensor, wherein the origin calibration sensor cooperates with the head vision system to detect the translational state of the ZR bonding head, and the force control sensor contacts the ZR bonding head to measure the downward pressure of the ZR bonding head; and a three-axis translation assembly that drives the bonding head assembly to translate in the X, Y, and Z directions; this application can achieve high-precision assembly between chips and carriers.

The application provides an integrated photonic wafer packaging structure with electromagnetic interference resistance, and relates to the technical field of chip packaging.The integrated photonic wafer packaging structure comprises an alumina ceramic sheet, electrically interconnected pins and ground removing pins are printed on the alumina ceramic sheet by a screen printing technology, the electrically interconnected pins and the ground removing pins are arranged at two ends of the alumina ceramic sheet respectively, a photonic wafer is connected to the alumina ceramic sheet between the electrically interconnected pins and the ground removing pins through a gold-tin eutectic bonding layer, the photonic wafers are isolated through a wafer isolation frame, and an electromagnetic shielding layer is electroplated on the wafer isolation frame.The electromagnetic shielding layer is designed, so that the packaged photonic wafer is miniaturized and secondary interference is eliminated.

This utility model discloses a windowed wafer, an infrared detector, and a thermal imaging device, applied in the field of infrared detection technology. It includes: a substrate; a support wall located on one side surface of the substrate, the support wall forming a cavity on one side of the substrate; an anti-overflow layer located at least on the surface of the support wall facing the cavity; and a solder layer located on the end face of the support wall, the solder layer contacting the anti-overflow layer; the wettability of the anti-overflow layer surface with the solder layer is greater than the wettability of the solder layer with the device wafer substrate. By providing an anti-overflow layer on the side wall of the support wall, since the wettability of the anti-overflow layer surface with the solder layer is greater than the wettability of the solder layer with the device wafer substrate, the surface of the anti-overflow layer acts as a solder climbing channel, providing a vertical climbing channel for the solder. Excess solder can climb along the side wall of the support wall, thereby solving the overflow problem in eutectic bonding technology during the bonding pressure process, which is beneficial for further reducing chip size.

This application discloses an electronic device and a method for manufacturing the same. An electronic device includes: a target substrate, an array of microsemiconductor structures, an array of bonding members, and a bonding layer. The array of microsemiconductor structures is disposed on the target substrate. The array of bonding members corresponds to the array of microsemiconductor structures and electrically connects the array of microsemiconductor structures to a patterned circuit on the target substrate; each pair of bonding members is independent of the others; each bonding member is an integral component formed by a conductive pad disposed on the target substrate and a conductive electrode disposed on each of the microsemiconductor structures through eutectic bonding. The bonding layer connects each microsemiconductor structure to the target substrate; wherein the bonding layer does not have a conductive material; each bonding member is contacted and covered by the bonding layer, and the bonding layer and the array of bonding members form a homolayer relationship.

The application discloses a DCB stator, a stator cooling structure and a permanent magnet motor, and belongs to the permanent magnet motor field.The DCB stator comprises a DCB substrate adopting a sandwich eutectic bonding structure of copper-ceramic-copper and a fractional concentrated winding.The fractional concentrated winding is a conductor structure directly formed on the upper and lower surfaces of the DCB substrate through a mask etching process and is used for transferring heat to an outer peripheral heat dissipation area of the DCB stator.The conductor structures on the upper and lower surfaces are electrically connected and fixed through a connecting copper strip distributed through the placement holes in the outer periphery of the DCB substrate.The DCB stator, the stator cooling structure and the permanent magnet motor are used to prepare an integral fractional concentrated winding stator with the DCB substrate adopting the copper-ceramic-copper eutectic bonding as a core, and are matched with a coaxial series type full-peripheral water-cooling structure, so that the power density, the operation efficiency and the structural reliability of the motor are greatly improved, the manufacturing process is simplified, and the mass industrial production is adapted.

Embodiments of the present application provide a manufacturing method of a display panel, the display panel and a display device, and relate to the technical field of display, and improve the transfer precision of light emitting elements. The manufacturing method comprises the following steps: providing a back plate; forming a bonding part on the back plate, the back plate comprising a first area and a second area surrounding the first area, and the bonding part being located in the first area; forming an auxiliary layer covering the back plate and the bonding part on the back plate, the auxiliary layer comprising a first part located in the first area and a second part located in the second area; releasing a light emitting element on the auxiliary layer, so that an electrode of the light emitting element is in contact with the first part to form a temporary back plate; placing the temporary back plate in a first preset condition, and under the first preset condition, the fluidity of the first part is greater than that of the second part; bonding the electrode and the bonding part to form a eutectic bonding layer, and placing the temporary back plate in a second preset condition, so that the first part forms a solid first part, and the second part forms a solid second part.

This invention discloses a highly reliable, pressure-free, ultra-low void ratio vacuum eutectic bonding method for chips, belonging to the field of microelectronic packaging and micro-assembly technology. The method includes the following steps: pre-treating the substrate to obtain a pre-substrate; picking up the chip and aligning it on the solder pads of the pre-substrate, ensuring the solder completely covers the chip's bonding surface, thus obtaining a bonding assembly; placing the bonding assembly into a vacuum eutectic furnace, and sequentially performing room-temperature nitrogen low-pressure pulse purging and replacement, heating, pre-eutectic holding, eutectic bonding, and nitrogen gradient pressurization and cooling treatment to complete the bonding; wherein, during the eutectic bonding process, vacuuming, micro-positive pressure under-bonding combined with high-frequency micro-pulses are used for solder filling. This method solves the problems of high void ratio, difficulty in controlling solder overflow, chip thermal damage, and complex operation steps existing in current chip vacuum eutectic bonding processes.