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122 results about "Bare surface" patented technology

Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof

The invention discloses a longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and a manufacturing method thereof. The device successively comprises a substrate (1), an n-type GaN layer (2), an electronic barrier layer (3), a non-doped GaN layer (4) and a heterostructure potential barrier layer (5) from bottom to top, wherein a groove is etched in the n-type GaN layer from the surface of the heterostructure potential barrier layer; a p-type GaN layer is formed on the groove by secondary growth so as to realize a grid conducting channel (7); two ends of the heterostructure potential barrier layer form source electrodes (9); an insulating layer (8) is covered on the grid conducting channel and the exposed surface of the heterostructure potential barrier layer; a grid electrode (11) is covered at a channel position on the insulating layer; and drain electrodes (10) are covered on the underside of the substrate. In the invention, a two-dimensional electron gas heterostructure with high concentration is taken as an access area, thus effectively reducing the on resistance; and the thin p-type GaN layer is formed in the etching groove by secondary growth, thus being easy to improve the threshold voltage and channel mobility of the longitudinally-conductive normally-closed MISFET.
Owner:SHANGHAI XINYUANJI SEMICON TECH

Thin film transistor and preparation method thereof, and array substrate

A thin film transistor and a preparation method thereof and an array substrate are provided, the thin film transistor includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, the gate is disposed on the substrate, the gate insulating layer covers the gate, the first metal layer includes a first electrode and a second electrode spaced apart on the gate insulating layer, the second metal layer includes a source and a drain spaced apart, one end of the active layer is sandwiched between the first electrode and thesource electrode, the other end of the active layer is sandwiched between the second electrode and the drain electrode, and the passivation layer covers the exposed surfaces of the source electrode, the drain electrode and the active layer. By sandwiching the active layer between the first metal layer and the second metal layer, the contact performance between the active layer and the second metallayer is improved. In the preparation method of the present invention, the first metal layer and the second metal layer are formed by two times ofa composition process, thereby avoiding the occurrence of a chamfer.
Owner:SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD

Device for thinning multi-layer material and method for thinning to-be-detected sample

InactiveCN102520212ASolving In-Situ Etch Control ProblemsScanning probe microscopyPotential differenceElectron microscope
The invention provides a device for thinning a multi-layer material and a method for thinning a to-be-detected sample, belonging to the field of testing of semiconductors. The device comprises a reaction chamber, an atomic force microscope, an electron microscope and a sample table. The sample table, the atomic force microscope and the electron microscope are positioned in the reaction chamber. The method for thinning the to-be-detected sample comprises the following steps of: putting a sample in the reaction chamber; measuring first contact potential difference V1 of a first bared surface of the to-be-detected sample; moving away a conducting probe of the atomic force microscope; etching the first bared surface at the depth X to expose a second surface; measuring first contact potential difference V2 of a second bared surface of the to-be-detected sample; and comparing the V1 with the V2 to judge whether to etch continuously. The device and the method disclosed by the invention are used for solving the problem of being incapable of precisely dissecting in the prior art. The device and the method are capable of precisely dissecting hetero-junction devices and have important meanings on preparation and property research of semiconductor devices.
Owner:SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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