Semiconductor packaging structure and packaging method thereof

A packaging structure and semiconductor technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of high cost, complicated process, and the thickness of the adapter board can not be too thick, so as to reduce the production cost , The effect of reducing the difficulty of the process

Active Publication Date: 2012-08-01
CHINA WAFER LEVEL CSP
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Problems solved by technology

[0004] However, in the existing interposer board packaging technology, due to the difficulty of the through-hole process of the interposer board, the interposer board cannot be too thick. In order to ensure its performance, the interposer is usually bonded by a temporar

Method used

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  • Semiconductor packaging structure and packaging method thereof
  • Semiconductor packaging structure and packaging method thereof
  • Semiconductor packaging structure and packaging method thereof

Examples

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[0045] With reference figure 2 , to introduce a specific implementation of the semiconductor packaging method of the present invention, the method specifically includes the following steps:

[0046]S1. Provide an adapter plate 10, which includes an upper surface 100a and a lower surface opposite to the upper surface 100a. The material of the adapter plate 10 can be selected from silicon, glass and other semiconductor process well-known to those of ordinary skill in the art. Substrate material, on the lower surface 100b of the adapter plate 10, form a plurality of blind holes extending to the upper surface 100a of the adapter plate to a certain depth, specifically: spin coat a layer of photoresist on the lower surface 100b of the adapter plate 10, and The photoresist-coated side is exposed through a pre-designed mask plate (not shown), and then the exposed photoresist is washed away by developing to expose part of the interposer 10 area; Etching or wet etching technology will...

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PUM

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Abstract

The invention discloses a semiconductor packaging structure and a semiconductor packaging method. The packaging structure comprises a chip, an adapter plate and a plurality of through holes, wherein a plurality of metal salient points are arranged on the chip; an accommodation space is sunken on the upper space of the adapter plate, and the chip is accommodated in the accommodation space; the through holes penetrate through the adapter plate, and are communicated with the accommodation space; a conductive medium is arranged in each through hole, and is electrically connected to a redistribution circuit on the lower surface of the adapter plate; a plurality of solder bumps are arranged on the redistribution circuit; the metal salient points are electrically connected with the conductive medium; and pitches between the solder bumps are greater than those between the metal salient points. The accommodation space capable of accommodating the chip is formed on the adapter plate, so that process difficulty in the packaging of the adapter plate is lowered, and production cost is further decreased.

Description

technical field [0001] The invention belongs to the technology in the field of semiconductor manufacturing, and in particular relates to a semiconductor packaging structure and a packaging method thereof. Background technique [0002] With the continuous development of semiconductor technology, the function of a single chip is becoming more and more powerful, but the size of the chip is getting smaller and smaller, and the number of I / O per unit area is correspondingly increasing. The emergence of the adapter board solves the problem. this problem. [0003] In the prior art, through-holes are usually formed on the adapter board through silicon via technology, and the circuit is rewired on the front side of the adapter board, the circuit is rewired on the back side, and bumps are made to match the size of the solder pads on the PCB board. To solve the problem of incompatibility with PCB. [0004] However, in the existing interposer board packaging technology, due to the dif...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L21/60
CPCH01L2224/16225
Inventor 王之奇喻琼俞国庆王蔚
Owner CHINA WAFER LEVEL CSP
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