30 results about "Partial thickness" patented technology

The utility model provides a collector plate, a battery and electric equipment. The flow collecting disc comprises a flow collecting disc body and a turnover piece, a through hole is formed in the flow collecting disc body, the turnover piece is arranged at the through hole, the turnover piece comprises a flow collecting part and a connecting part, the connecting part is connected with the flow collecting part and the flow collecting disc body, the partial thickness of the connecting part is smaller than the thickness of other parts of the connecting part, and / or the turnover piece is arranged on the flow collecting disc body. The thickness of at least part of the connecting part is smaller than that of the collector plate body, and / or the thickness of at least part of the connecting part is smaller than that of the collector part. According to the collector plate, the turnover piece is easier to turn over, the turnover angle of the turnover piece is guaranteed, and the unfolding effect of the collector plate is improved.

A forming method of a filter comprises the following steps: after forming a first mask for covering an initial electrode finger in an edge region, removing partial thickness of an initial interdigital electrode at the side part of a first mask layer, and forming a bus bar of a bus region and electrode fingers of a central region and the edge region, a piston structure located at the top of an electrode finger is formed at the intersection of the first mask layer and the electrode finger of the edge area; the first mask layer covers the initial electrode finger in the edge area, and the projection of the first mask layer on the substrate intersects with the projection of the initial electrode finger on the substrate, namely, the edge of the first mask layer is self-aligned with the side wall of the initial electrode finger in the edge area, so that the side wall of the piston structure is aligned with the side wall of the electrode finger; and the appearance quality of the interdigital electrode and the alignment precision of the electrode fingers and the piston structure are improved, so that the clutter suppression effect of the filter is improved.

A CMOS device and a method for fabricating the device are disclosed. In the method, an in-situ etch-back process is performed to form trenches in PFET regions, which extends through a partial thickness of the PFET region and exposes side wall of the STI structure. Subsequently, an in-situ epitaxial growth process is performed to form channel layer in the trenches. In this process, the side walls of the STI structures can block lateral growth of the channel layer in the trenches, overcoming the problem that the resulting channel layer may have a smaller thickness formed above edge areas of the PFET regions than formed above central areas thereof. In addition, before the channel layer is formed, the substrate is subjected to an in-situ pre-baking process, which removes moisture and contaminants in the trenches.

The invention provides a preparation method of a conductive interconnection structure, and the method comprises the steps: firstly etching a second hard mask layer and a part of thickness of a first hard mask layer to form a plurality of first openings and a plurality of second openings, and then carrying out the damascene etching according to the first openings and the second openings to form a first groove and a second groove, the bottom of the finally formed first groove is exposed out of the middle metal layer, and the bottom wall of the finally formed second groove is a curved surface which is low in the middle and high in the edge and keeps a certain distance from the bottom surface of the low-K dielectric layer. The bottom wall of the second groove is adjusted to be the curved surface with the low middle and the high edge, the field intensity distribution of the bottom of the second groove can be improved, meanwhile, the distance of diagonal corners (weak breakdown positions) between the upper layer metal and the lower layer metal can be increased, the condition of high-voltage breakdown of the diagonal corners between the upper layer metal and the lower layer metal is avoided, and the reliability of the device is improved. And thus, the TDDB reliability is improved.

A tendon repair implant for treatment of a partial thickness tear in the supraspinatus tendon of the shoulder is provided. The implant may incorporate features of rapid deployment and fixation by an arthroscopic means approach that compliment current procedures; tensile properties that result in desired sharing of anatomical load between the implant and native tendon during rehabilitation; selected porosity and longitudinal pathways for tissue in-growth; sufficient cyclic straining of the implant in the longitudinal direction to promote remodeling of new tissue to tendon-like tissue; and, may include a bioresorbable construction to provide transfer of additional load to new tendon-like tissue and native tendon over time.

The utility model discloses a PTFE special-shaped belt measuring device which comprises a base, the top of the base is fixedly connected with a fixing frame, the top of the fixing frame is provided with a feeding port, the lower top face of the fixing frame is fixedly connected with a pair of fixing blocks, the bottoms of the fixing blocks are fixedly connected with a positioning frame, the top of the positioning frame is provided with a material guiding port, and the two sides of the positioning frame are provided with positioning holes. A bolt is in threaded connection with the interior of the positioning hole, a sliding groove is formed in the fixing frame, and a measuring mechanism is installed on the fixing frame. According to the utility model, the thickness of the PTFE special-shaped belt can be measured without contact so as to prevent errors of the measured thickness caused by deformation of the PTFE special-shaped belt, the PTFE special-shaped belt can be suspended and fixed so as to prevent local thickness distortion caused by tilting or wrinkling in the thickness measurement process, the flexibility is good, and the measurement precision is high. The height position of the measuring mechanism can be adjusted according to the length size of the PTFE special-shaped belt, and the measuring mechanism can be detached and replaced when a fault occurs.

The invention provides a bonding wafer damage layer characterization method comprising the following steps: S1, providing a bonding wafer, forming a back surface oxide layer on the back surface of the bonding wafer, and forming a damage layer on the surface of the back surface oxide layer; s2, executing a first etching process to etch and remove a part of thickness of the damaged layer, and measuring the number of defects and the number of particles on the back surface of the bonded wafer after etching and the etching thickness d1 of the first etching process; s3, executing a cleaning process to remove surface particles of the bonding wafer; s4, executing a second etching process to etch the damaged layer, wherein the etching rate of the second etching process is smaller than that of the first etching process; and S4, circularly executing the step S4 until the measured number of defects on the back surface of the bonded wafer is kept stable. According to the method, the damaged layer of the wafer can be accurately represented, the thickness of the damaged layer can be accurately measured, and the defect density in the damaged layer can be represented.

The embodiment of the present disclosure provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate, wherein the substrate has a groove extending from the front surface to the back surface of the substrate; forming a flowable dielectric film filling the groove on the front surface of the substrate, and the top surface of the flowable dielectric film is higher than the front surface of the substrate; performing a first annealing treatment on the flowable dielectric film under a first temperature condition to form a first dielectric film; removing the first dielectric film with a partial thickness on the front surface of the substrate after the first annealing treatment; and performing a second annealing treatment on the remaining first dielectric film under a second temperature condition to form a second dielectric film, wherein the first temperature is lower than the second temperature. The semiconductor structure manufacturing method provided by the embodiment of the present disclosure is beneficial to improve the performance of the formed semiconductor structure.

According to the NORD flash memory device and the manufacturing method thereof provided by the invention, when the hard mask layer on the gate stack is patterned, the hard mask layer with partial thickness is reserved, and the first side wall is thinned, so that when the second side wall and the third side wall are formed by deposition and etching, the thickness of the second side wall is reduced, and the thickness of the third side wall is reduced. The position, where a defect point is prone to being generated, of the third side wall in the etching process is transferred to the vertex angle of the hard mask instead of the vertex angle of the control gate, and the problems that due to the fact that the etching process window of the first side wall is small, the third side wall is broken at the vertex angle of the control gate, and the top end of the third side wall is exposed after a word line polycrystalline silicon layer is ground and etched back are solved. Short circuit between the control gate and the word line is avoided, and device failure is further avoided.

The present invention provides a molded body in which fracturing occurs less readily at a burring structure part, said fracturing starting from surface damage of a root part of the burring structure part.　A molded body (1) according to the present invention is a steel molded body having a burring structure part (2) and a plate-like part (3) extending around the burring structure part (2), characterized in that the burring structure part (2) has a hole part (21) and a wall part (22) provided around the hole part (21) and having a leading edge part (22a) and a root part (22b), the root part (22b) has a plurality of band-like Mn segregation parts arranged at intervals in the thickness direction of the root part (22b) and extending in the surface direction of the root part (22b), the average spacing, in the thickness direction, of the band-like Mn segregation parts at a 1t / 4 position of the thickness t of the root part (22b) is between 4.0 μm and 20.0 μm, inclusive, and the Mn segregation strength of the band-like Mn segregation parts is between 2.00% and 3.50% by mass, inclusive.

The invention relates to the technical field of lasers, in particular to a preparation method of a low-power-consumption mid-infrared quantum cascade laser, and the method comprises the steps: providing an epitaxial wafer which comprises an initial lower waveguide layer, an active layer and an initial upper waveguide layer which are stacked in sequence; patterning processing is carried out on the epitaxial wafer with partial thickness to form a substrate and an initial ridge-shaped structure located on the substrate, a groove is formed in the side face of the initial ridge-shaped structure, and the initial ridge-shaped structure comprises a lower waveguide layer, an initial active region and an upper waveguide layer which are sequentially stacked in the direction away from the substrate; the initial active region is transversely etched through the groove so as to remove the initial active region with a part of width, the remaining initial active region serves as an active region, the width of the upper waveguide layer and the width of the lower waveguide layer are both larger than the width of the active region, and the lower waveguide layer, the active region and the upper waveguide layer form a ridge-shaped structure. According to the invention, the preparation difficulty of the quantum cascade laser with the narrow ridge is at least reduced, and a narrower active region can be prepared.

The invention relates to the technical field of wafer processing, in particular to a wafer stacking structure forming method and a wafer stacking structure. The forming method comprises the following steps: sequentially stacking N wafers to form a wafer stacking structure; the stacking of any ith wafer from the bottom to the top and the (i-1) th wafer comprises the following steps: trimming the partial thickness of the ith wafer inwards from the edge, so that the trimmed ith wafer forms a boss structure, the boss structure comprises a base body part and a boss part, and the horizontal size of the base body part is larger than that of the boss part; enabling the boss part to face the surface of the (i-1) th wafer, and forming a stacked intermediate with a tower-shaped structure with the (i-1) th wafer; the stacked intermediate is thinned, and the whole thickness of the base body part is removed; and repeating the steps until the (i = N) th wafer is stacked. According to the forming method, the tower-shaped structure instead of a columnar structure is finally formed, so that a large effective area of the wafer is saved, and the loss of the effective area of the wafer is reduced.

A semiconductor package structure and a method for manufacturing the same, wherein the semiconductor package structure comprises: a redistribution structure, the redistribution structure comprising a wiring layer, a cavity extending from a side surface of the redistribution structure to a partial thickness of the redistribution structure, and a bottom of the cavity exposing a partial wiring layer; a first chip flip-chip mounted on a side of the redistribution structure, the first chip having a first conductive member on a side of an active surface of the first chip, the first conductive member being located in the cavity and connected with the wiring layer at the bottom of the cavity, and an edge region of the active surface of the first chip being attached to a surface of the redistribution structure at a periphery of the cavity; and a molding layer covering the side of the redistribution structure and covering the first chip, the molding layer not being in contact with the active surface of the first chip. The semiconductor package structure can realize integration of a functional chip and other chips by using a fan-out process.

The application provides a preparation method of a memory, comprising the following steps: providing a substrate, wherein a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are sequentially stacked on the substrate; etching partial thicknesses of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer and the substrate to form a trench; forming a metal floating gate material layer in the trench, wherein the metal floating gate material layer covers the inner wall of the trench and extends to cover the hard mask layer; and performing a nitriding treatment on the metal floating gate material layer to repair ion vacancies in the metal floating gate material layer, form a stable metal compound crystal structure, prevent free metal ions from diffusing to affect the continuity of the metal floating gate material layer, and further ensure the continuity of a subsequently formed metal floating gate layer.

A method for forming a double-channel fin-type transistor comprises the steps that a substrate is provided, the substrate comprises a first region and a second region adjacent to the first region, a first fin portion is arranged on the top of the substrate in the first region in a protruding mode, a second fin portion is arranged on the top of the substrate in the second region in a protruding mode, and the etching rate of the first fin portion is smaller than that of the second fin portion; performing first modification treatment on the surfaces of the first fin part and the second fin part to enable the film deposition rate of the surface of the first fin part to be smaller than that of the surface of the second fin part; sacrificial liner layers are formed on the top and the side wall of the first fin part and the top and the side wall of the second fin part; forming an isolation material layer covering the first fin part, the second fin part and the sacrificial liner layer on the top of the substrate; and removing partial thickness of the isolation material layer, the sacrificial liner layer and partial thickness of the first fin part, taking the residual isolation material layer as an isolation structure, and exposing the side walls of the first fin part and the second fin part from the isolation structure. And the size uniformity of the first fin part and the second fin part is improved.

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate including a substrate and a fin material layer; etching a partial thickness of the fin material layer to form an initial fin, and the etching has a first etch rate ratio; etching a remaining fin material layer exposed by the initial fin to form a fin standing on the substrate, the fin including a bottom fin, a first portion fin and a second portion fin from bottom to top, the second portion fin and the first portion fin constituting an effective fin, and the etching the partial thickness of the fin material layer exposed by the initial fin has a second etch rate ratio, the second etch rate ratio is less than the first etch rate ratio, for making a bottom line width of the first portion fin less than a top line width of the first portion fin; forming an isolation layer covering a sidewall of the bottom fin and exposing the effective fin. The present application reduces leakage current and reduces the impact on the on-current, thereby improving the on-off current ratio of the transistor.

The invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, forming an oxide layer and a nitride layer on the substrate, etching the nitride layer, the oxide layer and a part of thickness of the substrate to form a shallow trench, and forming an isolation material layer which fills the shallow trench and covers the nitride layer; planarizing the isolation material layer to the remaining isolation material layer of partial thickness on the nitride layer; removing the residual isolation material layer on the nitride layer and the nitride layer to enable the upper surface of the oxide layer to be flush with the upper surface of the isolation material layer in the shallow trench; and removing the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure. According to the method, a flat surface is formed after the nitride layer is removed, and when the oxide layer is removed later, the flat surface can prevent the edge of the isolation material layer in the shallow trench from being subjected to transition etching, so that an edge groove is prevented from being formed at the top edge of the shallow trench isolation structure, and the performance of a device is improved.

The present application provides an InGaAs wafer and a manufacturing method therefor, and a radio frequency array chip and a manufacturing method therefor. The manufacturing method for the InGaAs wafer comprises: forming a donor substrate, wherein the donor substrate comprises a first substrate, an absorption layer, a first doped layer, and a bonding layer which are sequentially stacked, the absorption layer is made of InGaAs, the first doped layer is made of InGaAs or InP, the first substrate at least comprises a target layer, and the target layer is made of InP; forming an acceptor substrate, wherein the acceptor substrate comprises a first silicon substrate, a trap-rich layer, and an insulating layer which are sequentially stacked, and the trap-rich layer is an amorphous material composed of group IV elements; bonding the donor substrate to the acceptor substrate by making the bonding layer face the insulating layer; removing a partial thickness of the first substrate and retaining the target layer; and doping the target layer to obtain a second doped layer, thereby forming the InGaAs wafer. The trap-rich layer can trap free parasitic charges, thereby reducing parasitic capacitance, and thus improving the performance of the radio frequency array chip manufactured using the InGaAs wafer.

A segmented gasket includes multiple segments having partial thickness mating portions at ends thereof. The mating portions joinable via an adhesive and are configured to interlock the segments and to isolate the adhesive from the surface of the gasket. The segmented gasket may be provided in a kit with the detached segments and a pre-applied or separate adhesive.

The invention relates to a preparation method of a semiconductor structure. The preparation method comprises the following steps: forming a silicon oxide layer covering a first region and a second region; etching by adopting an anisotropic dry etching process to remove partial thickness of the silicon oxide layer in the second region, the first source region and the first drain region, and respectively forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region; forming a protective mask layer on the silicon oxide layer in the first region and on the side walls of the first groove and the second groove, wherein the protective mask layer exposes the remaining silicon oxide layer in the second region and at the bottoms of the first groove and the second groove; removing the residual silicon oxide layer in the second region and at the bottoms of the first groove and the second groove by adopting a wet etching process, and exposing the substrate surface of the second region, the first source region and the first drain region; a first gate electrode is formed on the silicon oxide layer in the first channel region. And the thickness uniformity of the silicon oxide layer on the first channel region is improved.

Embodiments disclosed herein include an apparatus with a component embedded in a core. Apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. In an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. In an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.

The invention discloses a semiconductor structure and a forming method thereof, and a packaging structure and method, and the semiconductor structure comprises a substrate which is provided with a dielectric layer; the metal layer is located in the dielectric layer with partial thickness, the dielectric layer is exposed out of the top surface of the metal layer, and the metal layer comprises a first metal layer and a second metal layer covering the first metal layer; the stress barrier structure protrudes from the first metal layer, the stress barrier structure divides the surface of the first metal layer into a plurality of areas, and the second metal layer covers the stress barrier structure; and the interconnection layer covers the metal layer and the dielectric layer. According to the invention, the device yield is improved.

The invention discloses a semiconductor device and a forming method thereof. The method comprises the following steps: providing a substrate; forming a sacrificial layer on the substrate; forming a first opening, wherein the first opening penetrates through the sacrificial layer and is located in a part of thickness of the substrate; forming a collector region in the first opening; forming a base region in the first opening on the collector region; forming an emitter region on the base region; removing the sacrificial layer to expose the side wall of the base region; and forming an outer base region on the substrate at two sides of the base region, wherein the outer base region is connected with the side wall of the base region. After the sacrificial layer is formed, directly forming a base region on the collector region; after the base region is formed, the sacrificial layer is removed, and the outer base regions connected with the side walls of the base region are formed on the substrate on the two sides of the base region, so that the base region is formed in the single direction, holes and defects in the base region can be effectively avoided, the contact resistance between the outer base regions and the base region is reduced, and the performance of the device is improved. And the performance of the semiconductor device is improved.

A tendon repair implant for treatment of a partial thickness tear in the supraspinatus tendon of the shoulder is provided. The implant may incorporate features of rapid deployment and fixation by an arthroscopic means approach that compliment current procedures; tensile properties that result in desired sharing of anatomical load between the implant and native tendon during rehabilitation; selected porosity and longitudinal pathways for tissue in-growth; sufficient cyclic straining of the implant in the longitudinal direction to promote remodeling of new tissue to tendon-like tissue; and, may include a bioresorbable construction to provide transfer of additional load to new tendon-like tissue and native tendon over time.

The present disclosure provides a condom that includes an elongated tube defined by an outer wall that includes an elastomeric material. The elongated tube may have a closed end and an open end. The elongated tube may have a tip portion that extends a distance from the closed end toward the open end and a shaft portion that extends from the open end to the tip portion. The outer wall in the tip portion has a tip portion thickness, and the outer wall in the shaft portion has a shaft portion thickness. A ratio of the tip portion thickness to the shaft portion thickness (T / S) is about 1.5 or greater.

A filter forming method, comprising: after forming a first mask layer covering initial electrode fingers in an edge region, removing a partial thickness of the initial interdigital electrode on the side of the first mask layer, forming a bus bar of a bus region, and electrode fingers of a center region and the edge region, and forming a piston structure on the top of the electrode fingers at the intersection of the first mask layer and the electrode fingers in the edge region; since the first mask layer covers the initial electrode fingers in the edge region, and the projection of the first mask layer on the substrate intersects with the projection of the initial electrode fingers on the substrate, that is, the edge of the first mask layer is self-aligned with the sidewall of the initial electrode fingers in the edge region, therefore, the sidewall of the piston structure is aligned with the sidewall of the electrode fingers, which is beneficial to improve the morphology quality of the interdigital electrode, and the alignment accuracy of the electrode fingers and the piston structure, thereby improving the function of the filter in suppressing spurs.

A semiconductor device and a method of forming the same. The forming method includes: providing a substrate, forming a dielectric layer on the top of the substrate, forming an opening in the dielectric layer, the opening penetrating the dielectric layer and extending into the substrate to a partial thickness; forming an optoelectronic layer in the opening; removing a partial thickness of the dielectric layer on the side of the optoelectronic layer, forming a trench surrounding the optoelectronic layer in the dielectric layer, and the trench exposing the optoelectronic layer; forming a covering layer covering the dielectric layer and the optoelectronic layer, and the covering layer also filling the trench. The formation of the trench increases the filling angle around the optoelectronic layer, correspondingly improves the filling effect of the covering layer between the dielectric layer and the optoelectronic layer, thereby reducing the probability of void defects generated in the covering layer, and further facilitating the improvement of the performance of the semiconductor device (for example, reliability performance).

A method for forming a semiconductor structure, the method comprising: providing a substrate including a substrate and discrete fin portions located on the substrate, a gate structure spanning the fin portions being formed on the substrate, a first hard mask layer being formed on the top of the gate structure, a second hard mask layer being formed on the first hard mask layer, the material hardness of the first hard mask layer being less than that of the second hard mask layer, an interlayer dielectric material layer covering the second hard mask layer being further formed on the substrate; removing a first portion of the thickness of the interlayer dielectric material layer to expose the second hard mask layer, and the remaining interlayer dielectric material layer covering the sidewalls of the first hard mask layer; removing a portion of the thickness of the second hard mask layer; after removing a portion of the thickness of the second hard mask layer, simultaneously removing a second portion of the thickness of the interlayer dielectric material layer, the remaining second hard mask layer and the first hard mask layer, and the remaining interlayer dielectric material layer serving as an interlayer dielectric layer, the interlayer dielectric layer covering a partial sidewall or the entire sidewall of the gate structure.

The invention provides a method for improving the morphology of a gate oxide layer, and the method comprises the steps: providing a semiconductor structure which comprises a substrate, a groove formed in the substrate, and a field oxide layer which is formed at the bottom and the side wall of the groove and extends to the surface of the substrate, and the field oxide layer is of an ONO stacked structure and comprises a bottom oxide layer, a middle nitride layer and a top oxide layer from the bottom to the top; forming a source polycrystalline silicon layer in the groove, wherein the thickness of the source polycrystalline silicon layer is smaller than the depth of the groove; etching to remove the exposed partial thickness top oxide layer above the source polycrystalline silicon layer; forming a tunneling oxide layer in the groove, wherein the sum of the thickness of the tunneling oxide layer and the thickness of the polycrystalline silicon layer is smaller than the depth of the groove; step-by-step etching is carried out to remove the exposed top oxide layer with the residual thickness above the tunneling oxide layer and the middle nitride layer and the bottom oxide layer below the top oxide layer; and forming a gate oxide layer on the surface of the tunneling oxide layer and the side wall of the groove. According to the invention, the problem that the morphology of the gate oxide layer formed by the existing method has defects is solved.

The utility model discloses a nursing special rehabilitation seat cushion after operation relates to rehabilitation seat cushion technical field, including bottom plate, the top fixedly connected with soft pad of bottom plate, the both sides in soft pad are all embedded with water box, and one side wall of two water boxes all is fixedly connected with water pipe, and fixedly connected with a plurality of arc conduits between two water pipes, and one side wall of one water box is installed with micro water pump, the utility model discloses nursing special rehabilitation seat cushion after operation, through setting bottom plate and soft pad, and the partial thickness of soft pad is thicker, can reduce the extrusion of hip when sitting with the help of soft pad, to reduce the extrusion of wound when sitting, the arc backrest of quick assembly that can be equipped is formed with the support to the back of user, reduces the extrusion of wound when sitting and the physical strength that needs when sitting personally, and the heating sheet that is equipped with on arc backrest can heat hot compress to waist and sacrum of user when leaning, and the eight acupoints of waist and sacrum are hot compressed, can promote the blood circulation of waist.