46 results about "Partial thickness" patented technology

The invention provides a collector plate, a battery and electric equipment. The flow collecting disc comprises a flow collecting disc body and a turnover piece, a through hole is formed in the flow collecting disc body, the turnover piece is arranged at the through hole, the turnover piece comprises a flow collecting part and a connecting part, the connecting part is connected with the flow collecting part and the flow collecting disc body, the partial thickness of the connecting part is smaller than the thickness of other parts of the connecting part, and / or the turnover piece is arranged on the flow collecting disc body. The thickness of at least part of the connecting part is smaller than that of the collector plate body, and / or the thickness of at least part of the connecting part is smaller than that of the collector part. According to the collector plate, the turnover piece is easier to turn over, the turnover angle of the turnover piece is guaranteed, and the unfolding effect of the collector plate is improved.

The utility model provides a collector plate, a battery and electric equipment. The flow collecting disc comprises a flow collecting disc body and a turnover piece, a through hole is formed in the flow collecting disc body, the turnover piece is arranged at the through hole, the turnover piece comprises a flow collecting part and a connecting part, the connecting part is connected with the flow collecting part and the flow collecting disc body, the partial thickness of the connecting part is smaller than the thickness of other parts of the connecting part, and / or the turnover piece is arranged on the flow collecting disc body. The thickness of at least part of the connecting part is smaller than that of the collector plate body, and / or the thickness of at least part of the connecting part is smaller than that of the collector part. According to the collector plate, the turnover piece is easier to turn over, the turnover angle of the turnover piece is guaranteed, and the unfolding effect of the collector plate is improved.

A forming method of a filter comprises the following steps: after forming a first mask for covering an initial electrode finger in an edge region, removing partial thickness of an initial interdigital electrode at the side part of a first mask layer, and forming a bus bar of a bus region and electrode fingers of a central region and the edge region, a piston structure located at the top of an electrode finger is formed at the intersection of the first mask layer and the electrode finger of the edge area; the first mask layer covers the initial electrode finger in the edge area, and the projection of the first mask layer on the substrate intersects with the projection of the initial electrode finger on the substrate, namely, the edge of the first mask layer is self-aligned with the side wall of the initial electrode finger in the edge area, so that the side wall of the piston structure is aligned with the side wall of the electrode finger; and the appearance quality of the interdigital electrode and the alignment precision of the electrode fingers and the piston structure are improved, so that the clutter suppression effect of the filter is improved.

A CMOS device and a method for fabricating the device are disclosed. In the method, an in-situ etch-back process is performed to form trenches in PFET regions, which extends through a partial thickness of the PFET region and exposes side wall of the STI structure. Subsequently, an in-situ epitaxial growth process is performed to form channel layer in the trenches. In this process, the side walls of the STI structures can block lateral growth of the channel layer in the trenches, overcoming the problem that the resulting channel layer may have a smaller thickness formed above edge areas of the PFET regions than formed above central areas thereof. In addition, before the channel layer is formed, the substrate is subjected to an in-situ pre-baking process, which removes moisture and contaminants in the trenches.

The invention provides a preparation method of a conductive interconnection structure, and the method comprises the steps: firstly etching a second hard mask layer and a part of thickness of a first hard mask layer to form a plurality of first openings and a plurality of second openings, and then carrying out the damascene etching according to the first openings and the second openings to form a first groove and a second groove, the bottom of the finally formed first groove is exposed out of the middle metal layer, and the bottom wall of the finally formed second groove is a curved surface which is low in the middle and high in the edge and keeps a certain distance from the bottom surface of the low-K dielectric layer. The bottom wall of the second groove is adjusted to be the curved surface with the low middle and the high edge, the field intensity distribution of the bottom of the second groove can be improved, meanwhile, the distance of diagonal corners (weak breakdown positions) between the upper layer metal and the lower layer metal can be increased, the condition of high-voltage breakdown of the diagonal corners between the upper layer metal and the lower layer metal is avoided, and the reliability of the device is improved. And thus, the TDDB reliability is improved.

A tendon repair implant for treatment of a partial thickness tear in the supraspinatus tendon of the shoulder is provided. The implant may incorporate features of rapid deployment and fixation by an arthroscopic means approach that compliment current procedures; tensile properties that result in desired sharing of anatomical load between the implant and native tendon during rehabilitation; selected porosity and longitudinal pathways for tissue in-growth; sufficient cyclic straining of the implant in the longitudinal direction to promote remodeling of new tissue to tendon-like tissue; and, may include a bioresorbable construction to provide transfer of additional load to new tendon-like tissue and native tendon over time.

The utility model discloses a PTFE special-shaped belt measuring device which comprises a base, the top of the base is fixedly connected with a fixing frame, the top of the fixing frame is provided with a feeding port, the lower top face of the fixing frame is fixedly connected with a pair of fixing blocks, the bottoms of the fixing blocks are fixedly connected with a positioning frame, the top of the positioning frame is provided with a material guiding port, and the two sides of the positioning frame are provided with positioning holes. A bolt is in threaded connection with the interior of the positioning hole, a sliding groove is formed in the fixing frame, and a measuring mechanism is installed on the fixing frame. According to the utility model, the thickness of the PTFE special-shaped belt can be measured without contact so as to prevent errors of the measured thickness caused by deformation of the PTFE special-shaped belt, the PTFE special-shaped belt can be suspended and fixed so as to prevent local thickness distortion caused by tilting or wrinkling in the thickness measurement process, the flexibility is good, and the measurement precision is high. The height position of the measuring mechanism can be adjusted according to the length size of the PTFE special-shaped belt, and the measuring mechanism can be detached and replaced when a fault occurs.

The invention discloses a metal gate filling method which comprises the steps that a high dielectric constant layer and a first material layer are sequentially deposited in a gate trench of a substrate structure, and the first material layer is formed on the surface of the high dielectric constant layer. And depositing a sacrificial layer in the gate trench based on the first material layer, and etching to remove a part of thickness of the sacrificial layer in the gate trench so as to expose a part of the first material layer on the side wall of the top of the gate trench. And sequentially etching and removing the exposed first material layer and the exposed high dielectric constant layer based on the exposed position of the first material layer to form a first opening. And removing the remaining sacrificial layer in the gate trench to form a second opening at the position where the remaining sacrificial layer is removed, the opening width of the first opening being greater than the opening width of the second opening. Therefore, the phenomenon that the bottom cannot be completely deposited due to the fact that the top of the gate trench is deposited too thick is avoided, cavities or gaps are effectively prevented from being formed in the bottom of the gate electrode, and the electrical performance of the gate electrode is improved.

The invention provides a bonding wafer damage layer characterization method comprising the following steps: S1, providing a bonding wafer, forming a back surface oxide layer on the back surface of the bonding wafer, and forming a damage layer on the surface of the back surface oxide layer; s2, executing a first etching process to etch and remove a part of thickness of the damaged layer, and measuring the number of defects and the number of particles on the back surface of the bonded wafer after etching and the etching thickness d1 of the first etching process; s3, executing a cleaning process to remove surface particles of the bonding wafer; s4, executing a second etching process to etch the damaged layer, wherein the etching rate of the second etching process is smaller than that of the first etching process; and S4, circularly executing the step S4 until the measured number of defects on the back surface of the bonded wafer is kept stable. According to the method, the damaged layer of the wafer can be accurately represented, the thickness of the damaged layer can be accurately measured, and the defect density in the damaged layer can be represented.

The embodiment of the present disclosure provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate, wherein the substrate has a groove extending from the front surface to the back surface of the substrate; forming a flowable dielectric film filling the groove on the front surface of the substrate, and the top surface of the flowable dielectric film is higher than the front surface of the substrate; performing a first annealing treatment on the flowable dielectric film under a first temperature condition to form a first dielectric film; removing the first dielectric film with a partial thickness on the front surface of the substrate after the first annealing treatment; and performing a second annealing treatment on the remaining first dielectric film under a second temperature condition to form a second dielectric film, wherein the first temperature is lower than the second temperature. The semiconductor structure manufacturing method provided by the embodiment of the present disclosure is beneficial to improve the performance of the formed semiconductor structure.

According to the NORD flash memory device and the manufacturing method thereof provided by the invention, when the hard mask layer on the gate stack is patterned, the hard mask layer with partial thickness is reserved, and the first side wall is thinned, so that when the second side wall and the third side wall are formed by deposition and etching, the thickness of the second side wall is reduced, and the thickness of the third side wall is reduced. The position, where a defect point is prone to being generated, of the third side wall in the etching process is transferred to the vertex angle of the hard mask instead of the vertex angle of the control gate, and the problems that due to the fact that the etching process window of the first side wall is small, the third side wall is broken at the vertex angle of the control gate, and the top end of the third side wall is exposed after a word line polycrystalline silicon layer is ground and etched back are solved. Short circuit between the control gate and the word line is avoided, and device failure is further avoided.

To provide a cutter for incision of quadriceps tendon horizontally by a certain thickness.SOLUTION: Provided is a cutter having a U-shape, having an outside dimension with a constant width, having an inside dimension of a thickness of a quadriceps tendon to be subjected to incision, having one end being a sharp blade for incision, having another end being a thick surface, and having a center portion to be gripped with an existing handle.SELECTED DRAWING: Figure 4

The invention discloses a preparation method of an epitaxial structure. The preparation method of the epitaxial structure comprises the following steps: forming a stripping layer on one side of a substrate; an epitaxial layer is formed on the side, away from the substrate, of the stripping layer, and the decomposition temperature of the stripping layer is smaller than that of the epitaxial layer; decomposing the stripping layer to enable the stripping layer to be completely separated from the epitaxial layer; or decomposing the stripping layer and reserving a part of thickness of the stripping layer on the epitaxial layer. According to the invention, the substrate can be stripped on the basis of damage as little as possible or no damage to the epitaxial layer.

The present invention provides a molded body in which fracturing occurs less readily at a burring structure part, said fracturing starting from surface damage of a root part of the burring structure part.　A molded body (1) according to the present invention is a steel molded body having a burring structure part (2) and a plate-like part (3) extending around the burring structure part (2), characterized in that the burring structure part (2) has a hole part (21) and a wall part (22) provided around the hole part (21) and having a leading edge part (22a) and a root part (22b), the root part (22b) has a plurality of band-like Mn segregation parts arranged at intervals in the thickness direction of the root part (22b) and extending in the surface direction of the root part (22b), the average spacing, in the thickness direction, of the band-like Mn segregation parts at a 1t / 4 position of the thickness t of the root part (22b) is between 4.0 μm and 20.0 μm, inclusive, and the Mn segregation strength of the band-like Mn segregation parts is between 2.00% and 3.50% by mass, inclusive.

The invention relates to the technical field of lasers, in particular to a preparation method of a low-power-consumption mid-infrared quantum cascade laser, and the method comprises the steps: providing an epitaxial wafer which comprises an initial lower waveguide layer, an active layer and an initial upper waveguide layer which are stacked in sequence; patterning processing is carried out on the epitaxial wafer with partial thickness to form a substrate and an initial ridge-shaped structure located on the substrate, a groove is formed in the side face of the initial ridge-shaped structure, and the initial ridge-shaped structure comprises a lower waveguide layer, an initial active region and an upper waveguide layer which are sequentially stacked in the direction away from the substrate; the initial active region is transversely etched through the groove so as to remove the initial active region with a part of width, the remaining initial active region serves as an active region, the width of the upper waveguide layer and the width of the lower waveguide layer are both larger than the width of the active region, and the lower waveguide layer, the active region and the upper waveguide layer form a ridge-shaped structure. According to the invention, the preparation difficulty of the quantum cascade laser with the narrow ridge is at least reduced, and a narrower active region can be prepared.

To provide a wire gauze for construction capable of reducing the thickness of a part where the wire gauze for construction overlaps.SOLUTION: A wire gauze for construction 1 which is embedded in concrete Ct of a slab includes a plurality of linear parts 11, 12, 13 including linear parts extending in different directions on the same plane. The linear parts extending in different directions on the same plane among the plurality of linear parts 11, 12, 13 intersect on the same plane to form a plurality of intersection parts Cr1. An outer edge 1E of the wire gauze for construction 1 is a polygon including a part of the plurality of linear parts 11, 12, 13 and a part of the plurality of intersection parts Cr1, and at least one corner Cn1 of the outer edge 1E forms an angle of 120°.SELECTED DRAWING: Figure 4

To suppress thickness differences from occurring on a ground wafer partially.SOLUTION: In a holding surface correction processing step, an etching mechanism 40 corrects a shape of a holding surface 22 so that the shape has a surface shape similar to a surface shape of an upper surface of a wafer for trial-grinding ground in a trial-grinding step. This enables a holding part 21 of a chuck table 20 to be communicated with a suction source 201, in a grinding step, so that when the holding surface 22 suctions and holds a product wafer, the holding surface 22 becomes a substantially flat surface and a radial part of the holding surface 22 becomes parallel to a lower surface of a wafer grinding stone, which can suppress thickness differences from occurring partially on the product wafer ground by the wafer grinding stone. This enables the product wafer to be ground in an equal thickness.SELECTED DRAWING: Figure 7

The invention relates to the technical field of wafer processing, in particular to a wafer stacking structure forming method and a wafer stacking structure. The forming method comprises the following steps: sequentially stacking N wafers to form a wafer stacking structure; the stacking of any ith wafer from the bottom to the top and the (i-1) th wafer comprises the following steps: trimming the partial thickness of the ith wafer inwards from the edge, so that the trimmed ith wafer forms a boss structure, the boss structure comprises a base body part and a boss part, and the horizontal size of the base body part is larger than that of the boss part; enabling the boss part to face the surface of the (i-1) th wafer, and forming a stacked intermediate with a tower-shaped structure with the (i-1) th wafer; the stacked intermediate is thinned, and the whole thickness of the base body part is removed; and repeating the steps until the (i = N) th wafer is stacked. According to the forming method, the tower-shaped structure instead of a columnar structure is finally formed, so that a large effective area of the wafer is saved, and the loss of the effective area of the wafer is reduced.

A semiconductor package structure and a method for manufacturing the same, wherein the semiconductor package structure comprises: a redistribution structure, the redistribution structure comprising a wiring layer, a cavity extending from a side surface of the redistribution structure to a partial thickness of the redistribution structure, and a bottom of the cavity exposing a partial wiring layer; a first chip flip-chip mounted on a side of the redistribution structure, the first chip having a first conductive member on a side of an active surface of the first chip, the first conductive member being located in the cavity and connected with the wiring layer at the bottom of the cavity, and an edge region of the active surface of the first chip being attached to a surface of the redistribution structure at a periphery of the cavity; and a molding layer covering the side of the redistribution structure and covering the first chip, the molding layer not being in contact with the active surface of the first chip. The semiconductor package structure can realize integration of a functional chip and other chips by using a fan-out process.

The application provides a preparation method of a memory, comprising the following steps: providing a substrate, wherein a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are sequentially stacked on the substrate; etching partial thicknesses of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer and the substrate to form a trench; forming a metal floating gate material layer in the trench, wherein the metal floating gate material layer covers the inner wall of the trench and extends to cover the hard mask layer; and performing a nitriding treatment on the metal floating gate material layer to repair ion vacancies in the metal floating gate material layer, form a stable metal compound crystal structure, prevent free metal ions from diffusing to affect the continuity of the metal floating gate material layer, and further ensure the continuity of a subsequently formed metal floating gate layer.

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate; a plurality of first grooves positioned in the first region and a plurality of second grooves positioned in the second region are formed in the substrate; forming a rewiring layer which covers the first groove, naturally extends to the surface of the substrate and forms a first opening, and covers the second groove, naturally extends to the surface of the substrate and forms a second opening; wherein the area proportion of the first opening in the first region is greater than the area proportion of the second opening in the second region; a first dielectric layer is formed, the first dielectric layer covers the rewiring layer, and the first dielectric layer fills the first opening and the second opening; nitriding the first dielectric layer so that the first dielectric layer with a partial thickness is converted into a nitride layer; forming a second dielectric layer on the surface of the nitride layer; and photoetching the second dielectric layer and the first dielectric layer to expose part of the surface of the rewiring layer in the first region.

A method for forming a double-channel fin-type transistor comprises the steps that a substrate is provided, the substrate comprises a first region and a second region adjacent to the first region, a first fin portion is arranged on the top of the substrate in the first region in a protruding mode, a second fin portion is arranged on the top of the substrate in the second region in a protruding mode, and the etching rate of the first fin portion is smaller than that of the second fin portion; performing first modification treatment on the surfaces of the first fin part and the second fin part to enable the film deposition rate of the surface of the first fin part to be smaller than that of the surface of the second fin part; sacrificial liner layers are formed on the top and the side wall of the first fin part and the top and the side wall of the second fin part; forming an isolation material layer covering the first fin part, the second fin part and the sacrificial liner layer on the top of the substrate; and removing partial thickness of the isolation material layer, the sacrificial liner layer and partial thickness of the first fin part, taking the residual isolation material layer as an isolation structure, and exposing the side walls of the first fin part and the second fin part from the isolation structure. And the size uniformity of the first fin part and the second fin part is improved.

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate including a substrate and a fin material layer; etching a partial thickness of the fin material layer to form an initial fin, and the etching has a first etch rate ratio; etching a remaining fin material layer exposed by the initial fin to form a fin standing on the substrate, the fin including a bottom fin, a first portion fin and a second portion fin from bottom to top, the second portion fin and the first portion fin constituting an effective fin, and the etching the partial thickness of the fin material layer exposed by the initial fin has a second etch rate ratio, the second etch rate ratio is less than the first etch rate ratio, for making a bottom line width of the first portion fin less than a top line width of the first portion fin; forming an isolation layer covering a sidewall of the bottom fin and exposing the effective fin. The present application reduces leakage current and reduces the impact on the on-current, thereby improving the on-off current ratio of the transistor.

The invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, forming an oxide layer and a nitride layer on the substrate, etching the nitride layer, the oxide layer and a part of thickness of the substrate to form a shallow trench, and forming an isolation material layer which fills the shallow trench and covers the nitride layer; planarizing the isolation material layer to the remaining isolation material layer of partial thickness on the nitride layer; removing the residual isolation material layer on the nitride layer and the nitride layer to enable the upper surface of the oxide layer to be flush with the upper surface of the isolation material layer in the shallow trench; and removing the oxide layer and the isolation material layer flush with the oxide layer in the shallow trench to form a shallow trench isolation structure. According to the method, a flat surface is formed after the nitride layer is removed, and when the oxide layer is removed later, the flat surface can prevent the edge of the isolation material layer in the shallow trench from being subjected to transition etching, so that an edge groove is prevented from being formed at the top edge of the shallow trench isolation structure, and the performance of a device is improved.

The present application provides an InGaAs wafer and a manufacturing method therefor, and a radio frequency array chip and a manufacturing method therefor. The manufacturing method for the InGaAs wafer comprises: forming a donor substrate, wherein the donor substrate comprises a first substrate, an absorption layer, a first doped layer, and a bonding layer which are sequentially stacked, the absorption layer is made of InGaAs, the first doped layer is made of InGaAs or InP, the first substrate at least comprises a target layer, and the target layer is made of InP; forming an acceptor substrate, wherein the acceptor substrate comprises a first silicon substrate, a trap-rich layer, and an insulating layer which are sequentially stacked, and the trap-rich layer is an amorphous material composed of group IV elements; bonding the donor substrate to the acceptor substrate by making the bonding layer face the insulating layer; removing a partial thickness of the first substrate and retaining the target layer; and doping the target layer to obtain a second doped layer, thereby forming the InGaAs wafer. The trap-rich layer can trap free parasitic charges, thereby reducing parasitic capacitance, and thus improving the performance of the radio frequency array chip manufactured using the InGaAs wafer.

A segmented gasket includes multiple segments having partial thickness mating portions at ends thereof. The mating portions joinable via an adhesive and are configured to interlock the segments and to isolate the adhesive from the surface of the gasket. The segmented gasket may be provided in a kit with the detached segments and a pre-applied or separate adhesive.

A lens for refractive tear shaping, including a curved lens body defining an anterior partial thickness cavity indented into its anterior surface. The anterior partial thickness cavity has an anterior facing tear shaping surface structured to form a tear lens within the anterior partial thickness cavity. The anterior partial thickness cavity is structured to define a tear lens within the anterior partial thickness cavity by interaction between a tear film of the eye and the anterior facing base tear shaping surface. The posterior curvature of the tear lens is dependent on the shape of the anterior facing base tear shaping surface.

The invention discloses a metal 3D printing method and device, and relates to the technical field of 3D printing. The metal 3D printing method comprises the following steps: melting metal powder on a metal substrate by adopting a continuous laser beam emitted by a continuous laser to form a first cladding layer of at least partial area; and impacting the first cladding layer by adopting a pulse laser beam emitted by a pulse laser, and melting at least part of thickness of the first cladding layer to form a first metal layer. According to the embodiment of the invention, the pulse laser is used for carrying out laser shock on the first cladding layer, shock waves generated after high-temperature ionization enable the first cladding layer to generate plastic deformation, residual stress in the first cladding layer is reduced, dislocation density is increased, grains of a surface material are refined, and the surface of the formed first metal layer is smooth.

The invention relates to a preparation method of a semiconductor structure. The preparation method comprises the following steps: forming a silicon oxide layer covering a first region and a second region; etching by adopting an anisotropic dry etching process to remove partial thickness of the silicon oxide layer in the second region, the first source region and the first drain region, and respectively forming a first groove and a second groove in the silicon oxide layer in the first source region and the first drain region; forming a protective mask layer on the silicon oxide layer in the first region and on the side walls of the first groove and the second groove, wherein the protective mask layer exposes the remaining silicon oxide layer in the second region and at the bottoms of the first groove and the second groove; removing the residual silicon oxide layer in the second region and at the bottoms of the first groove and the second groove by adopting a wet etching process, and exposing the substrate surface of the second region, the first source region and the first drain region; a first gate electrode is formed on the silicon oxide layer in the first channel region. And the thickness uniformity of the silicon oxide layer on the first channel region is improved.

Embodiments disclosed herein include an apparatus with a component embedded in a core. Apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. In an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. In an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.