Product
Patsnap Eureka
For R&D, Patsnap Eureka makes reading and utilizing patents & technical documents easy.
Patsnap Eureka AIR
Designed for self-driven R&D workflows. Generate viable solutions, solve complex R&D challenges, empower your innovation with AI.
Patsnap Eureka Materials
Designed for material experts only. Revolutionize your material R&D, from search, analyze, to developing new materials.
Feature
TechResearch
Generate reliable direction feasibility study reports for your R&D in just a few steps.
TechSeek
Discover and master advanced knowledge NOW. Basics, ideas, possibilities, all at once.
TechMind
As an expert in R&D Theories, TechMind can generates customized viable solutions instantly.
TechRisk
Analyze your overall solution with one click, know your potential R&D risks in advance.
TechMonitor
Get weekly tech updates, stay abreast of the latest tech innovations and key insights.
Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
538 results about "Electroless deposition" patented technology
Efficacy Topic
Property
Owner
Technical Advancement
Application Domain
Technology Topic
Technology Field Word
Patent Country/Region
Patent Type
Patent Status
Application Year
Inventor
Process for forming cobalt and cobalt silicide materials in copper contact applications
InactiveUS20080268635A1Semiconductor/solid-state device manufacturingChemical vapor deposition coatingElectroless depositionCopper
Embodiments of the invention described herein generally provide methods for forming cobalt silicide layers and metallic cobalt layers by using various deposition processes and annealing processes. In one embodiment, a method for forming a cobalt silicide material on a substrate is provided which includes treating the substrate with at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material over the silicon-containing surface, and depositing a copper material over the cobalt silicide material. In another embodiment, a metallic cobalt material may be deposited over the cobalt silicide material prior to depositing the copper material. In one example, the copper material may be formed by depositing a copper seed layer and a copper bulk layer on the substrate. The copper seed layer may be deposited by a PVD process and the copper bulk layer may be deposited by an ECP process or an electroless deposition process.
Owner:APPLIED MATERIALS INC
Integrated electroless deposition system
InactiveUS20060033678A1Static indicating devicesSemiconductor/solid-state device manufacturingRutheniumEngineering
Embodiments of the invention provide a cluster tool configured to deposit a material onto a substrate surface by using one or more electroless, electrochemical plating, CVD and / or ALD processing chambers. In one aspect, a ruthenium-containing catalytic layer is formed. Embodiments of the invention provide a hybrid deposition system configured to deposit a seed layer on a substrate with an electroless process and to subsequently fill interconnect features on the substrate with an ECP cell. Other aspects provide an electroless deposition system configured to deposit a seed layer on a substrate, fill interconnect features on a substrate, or sequentially deposit both a seed layer and fill interconnect features on the substrate. One embodiment provides an electroless deposition system configured to form a capping layer over substrate interconnects. The system includes a vapor dryer for pre- and post-deposition cleaning of substrates as well as a brush box chamber for post-deposition cleaning.
Owner:APPLIED MATERIALS INC
Method of electroless plating copper on nitride barrier
InactiveUS6436816B1Insulating substrate metal adhesion improvementSolid-state devicesCopper platingElectroless deposition
A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.
Owner:TAIWAN SEMICON MFG CO LTD
Contact metallization scheme using a barrier layer over a silicide layer
ActiveUS20060251800A1Material nanotechnologySemiconductor/solid-state device detailsDevice materialElectroless deposition
Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and / or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and / or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.
Owner:APPLIED MATERIALS INC
Electroless deposition process on a silicon contact
ActiveUS20060264043A1Material nanotechnologySemiconductor/solid-state device manufacturingSalicideAlloy
Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
Owner:APPLIED MATERIALS INC
Integrated electroless deposition system
InactiveUS20070111519A1Electrolysis componentsSemiconductor/solid-state device manufacturingEngineeringElectroless deposition
Embodiments of the invention provide methods for depositing a material onto a surface of a substrate by using one or more electroless, electrochemical plating, CVD and / or ALD processes. Embodiments of the invention provide a method for depositing a seed layer on a substrate with an electroless process and to subsequently fill interconnect features on the substrate with an ECP process on a single substrate processing platform. Other aspects provide a method for depositing a seed layer on a substrate, fill interconnect features on a substrate, or sequentially deposit both a seed layer and fill interconnect features on the substrate. One embodiment provides a method for forming a capping layer over substrate interconnects. Methods include the use of a vapor dryer for pre- and post-deposition cleaning of substrates as well as a brush box chamber for post-deposition cleaning.
Owner:APPLIED MATERIALS INC
Electroless deposition processes and compositions for forming interconnects
InactiveUS20060252252A1Material nanotechnologySemiconductor/solid-state device detailsHydrogen fluorideTungstate
In one embodiment, a method for depositing a material on a substrate is provided which includes positioning a substrate containing a contact within a process chamber, exposing the substrate to at least one pretreatment step and depositing a fill the contact vias by an electroless deposition process. The pretreatment step contains multiple processes for exposing the substrate to a wet-clean solution, a hydrogen fluoride solution, a tungstate solution, a palladium activation solution, an acidic rinse solution, a complexing agent solution or combinations thereof. Generally, the HARC via contains a tungsten oxide surface and the shallow contact via may contain a tungsten silicide surface. In some example, the substrate is pretreated such that both vias are filled at substantially the same time by a nickel-containing material through an electroless deposition process.
Owner:APPLIED MATERIALS INC
Method of selectively depositing a thin film material at a semiconductor interface
InactiveUS20070108404A1Detergent mixture composition preparationSemiconductor/solid-state device manufacturingDevice formMetal silicide
Owner:APPLIED MATERIALS INC
Electroless deposition apparatus
An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.
Owner:APPLIED MATERIALS INC
Method and apparatus for forming device features in an integrated electroless deposition system
InactiveUS20070071888A1Growth inhibitionPrinted circuit aspectsSemiconductor/solid-state device manufacturingMaterial removalEngineering
Embodiments of the invention generally provide a cluster tool that is configured to electrolessly fill features formed on a substrate. More particularly, embodiments of the invention are used to integrate the filling of an interconnect or contact level feature using an electroless fill process and material removal steps. A typical sequence for forming an interconnect includes depositing one or more non-conductive layers, etching at least one of the layer(s) to form one or more features therein, depositing a barrier layer in the feature(s) and depositing one or more conductive layers, such as copper, to fill the feature.
Owner:APPLIED MATERIALS INC
Electroless deposition process on a silicide contact
InactiveUS20060246217A1Material nanotechnologySemiconductor/solid-state device manufacturingSalicideElectroless deposition
Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.
Owner:APPLIED MATERIALS INC
Apparatus for electroless deposition
ActiveUS7341633B2Liquid surface applicatorsVacuum evaporation coatingElectroless depositionEngineering
Embodiments of the invention generally provide a fluid processing platform. The platform includes a mainframe having a substrate transfer robot, at least one substrate cleaning cell on the mainframe, and at least one processing enclosure. The processing enclosure includes a gas supply positioned in fluid communication with an interior of the processing enclosure, a first fluid processing cell positioned in the enclosure, a first substrate head assembly positioned to support a substrate for processing in the first fluid processing cell, a second fluid processing cell positioned in the enclosure, a second head assembly positioned to support a substrate for processing in the second fluid processing cell, and a substrate shuttle positioned between the first and second fluid processing cells and being configured to transfer substrates between the fluid processing cells and the mainframe robot.
Owner:APPLIED MATERIALS INC
Electroless plating processes
InactiveUS6861097B1Reducing problem encounteredSimple methodPaper/cardboard articlesDecorative surface effectsPolymeric surfaceOxidation state
The invention includes processes for combined polymer surface treatment and metal deposition. Processes of the invention include forming an aqueous solution containing a metal activator, such as an oxidized species of silver, cobalt, ruthenium, cerium, iron, manganese, nickel, rhodium, or vanadium. The activator can be suitably oxidized to a higher oxidation state electrochemically. Exposing a part to be plated (such as an organic resin, e.g. a printed circuit board substrate) to the solution enables reactive hydroxyl species (e.g. hydroxyl radicals) to be generated and to texture the polymer surface. Such texturing facilitates good plated metal adhesion. As part of this contacting process sufficient time is allowed for both surface texturing to take place and for the oxidized metal activator to adsorb onto said part. The part is then contacted with a reducing agent capable of reducing the metal activator to a lower ionic form, or a lower oxidation state. That reduction can result in the formation of metallic catalytic material over the surface of the part. The reduced metal activator can then function to catalyze the electroless deposition of metal such as copper from solution by contacting the part with the plating solution.
Owner:SHIPLEY CO LLC
Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors
InactiveUS6465334B1Semiconductor/solid-state device manufacturingSemiconductor devicesElectroless depositionOxygen
High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and / or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate / gate insulator interface.
Owner:GLOBALFOUNDRIES US INC
Multilayer ceramic capacitor with terminal formed by electroless plating
InactiveUS7345868B2High strengthFixed capacitor electrodesFixed capacitor dielectricElectrolysisCeramic capacitor
A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.
Owner:PRESIDIO COMPONENTS
Process for electroless copper deposition
InactiveUS20070099422A1Solid-state devicesSemiconductor/solid-state device manufacturingCopper platingRuthenium
Embodiments of the invention provide a method for depositing a copper material on a substrate by an electroless deposition process and also provide a composition of an electroless deposition solution. In one embodiment, the copper material is deposited from an electroless copper solution that contains an additive, such as an inhibitor, to promote a bottom-up fill process. In one aspect, the field of the substrate may be maintained free of copper material or substantially free of copper material during the electroless deposition process. Prior to the electroless deposition process for forming the copper material, a barrier layer may be deposited on the substrate, and thereafter, a ruthenium layer may be deposited thereon. In one example, the copper material is formed during a bottom-up, electroless deposition process directly on the ruthenium layer. Alternatively, a seed layer may be formed on the ruthenium layer prior to depositing the copper material.
Owner:APPLIED MATERIALS INC
Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers
InactiveUS20050085031A1Semiconductor/solid-state device manufacturingLiquid/solution decomposition chemical coatingDevice materialAlloy
Embodiments of the invention generally provide compositions of activation-alloy solutions, methods to deposit activation-alloys and electronic devices including activation-alloys and capping layers. In one embodiment, a method for depositing a capping layer for a semiconductor device is provided which includes exposing a conductive layer on a substrate surface to an activation-alloy solution, forming an activation-alloy layer on the conductive layer using the activation-alloy solution, and depositing the capping layer on the activation-alloy layer using an electroless deposition solution.
Owner:APPLIED MATERIALS INC
Photovoltaic contact and wiring formation
InactiveUS20070148336A1Reduce contact resistanceEnhanced vapor depositionVacuum evaporation coatingSputtering coatingEtchingGas phase
A method and apparatus for fabricating a solar cell and forming metal contact is disclosed. Solar cell contact and wiring is formed by depositing a thin film stack of a first metal material and a second metal material as an initiation layer or seed layer for depositing a bulk metal layer in conjunction with additional sheet processing, photolithography, etching, cleaning, and annealing processes. In one embodiment, the thin film stack for forming metal silicide with reduced contact resistance over the sheet is deposited by sputtering or physical vapor deposition. In another embodiment, the bulk metal layer for forming metal lines and wiring is deposited by sputtering or physical vapor deposition. In an alternative embodiment, electroplating or electroless deposition is used to deposit the bulk metal layer.
Owner:APPLIED MATERIALS INC
Multilayer ceramic capacitor with terminal formed by electroless plating
InactiveUS20080158774A1High strengthFixed capacitor electrodesFixed capacitor dielectricCeramic capacitorElectroless deposition
Owner:PRESIDIO COMPONENTS
Methods and system for processing a microelectronic topography
InactiveUS6881437B2Avoid flowHigh boiling pointSemiconductor/solid-state device manufacturingPretreated surfacesElectroless depositionTopography
Methods and systems are provided which are adapted to process a microelectronic topography, particularly in association with an electroless deposition process. In general, the methods may include loading the topography into a chamber, closing the chamber to form an enclosed area, and supplying fluids to the enclosed area. In some embodiments, the fluids may fill the enclosed area. In addition or alternatively, a second enclosed area may be formed about the topography. As such, the provided system may be adapted to form different enclosed areas about a substrate holder. In some cases, the method may include agitating a solution to minimize the accumulation of bubbles upon a wafer during an electroless deposition process. As such, the system provided herein may include a means for agitating a solution in some embodiments. Such a means for agitation may be distinct from the inlet / s used to supply the solution to the chamber.
Owner:LAM RES CORP
Metallic structures incorporating bioactive materials and methods for creating the same
ActiveUS20060062820A1Reduce riskStructuredMaterial nanotechnologySurgeryInsertion stentElectroless deposition
Disclosed herein are methods to create medical devices and medical devices including bioactive composite structures. The methods include using template-assisted electro- or electroless deposition or codeposition methods for providing implantable medical devices coated with bioactive composite structures and also include layering deposited or codeposited metal layers with layers of bioactive materials. In one use, the implantable medical devices of the present invention include stents with bioactive composite structure coatings.
Owner:CELONOVA BIOSCIENCES INC
Methods of forming a semiconductor device including buried bit lines
ActiveUS20070295995A1Solid-state devicesSemiconductor/solid-state device manufacturingBit lineMetal silicide
A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.
Owner:SAMSUNG ELECTRONICS CO LTD
Apparatus and method for electroless deposition of materials on semiconductor substrates
InactiveUS6913651B2Simple and compact structureReduce manufacturing costLiquid surface applicatorsSpraying apparatusEngineeringElectroless deposition
An apparatus of the invention has a closable chamber that can be sealed and is capable of withstanding an increased pressure and high temperature. The chamber contains a substrate holder that can be rotated around a vertical axis, and an edge-grip mechanism inside the substrate holder. The deposition chamber has several inlet ports for the supply of various process liquids, such as deposition solutions, DI water for rinsing, etc., and a port for the supply of a gas under pressure. The apparatus is also provided with reservoirs and tanks for processing liquids and gases, as well as with a solution heater and a control system for controlling temperature and pressure in the chamber. The heater can be located outside the working chamber or built into the substrate holder, or both heaters can be used simultaneously. Uniform deposition is achieved by carrying out the deposition process under pressure and under temperature slightly below the boiling point of the solution. The solution can be supplied from above via a shower head formed in the cover, or through the bottom of the chamber. Rinsing or other auxiliary solutions are supplied via a radially moveable chemical dispensing arm that can be arranged above the substrate parallel thereto.
Owner:LAM RES CORP
Apparatus for electroless deposition of metals onto semiconductor substrates
InactiveUS20050263066A1Efficient depositionMinimal defectSpraying apparatusPretreated surfacesRobot positionEngineering
An electroless deposition system is provided. The system includes a processing mainframe, at least one substrate cleaning station positioned on the mainframe, and an electroless deposition station positioned on the mainframe. The electroless deposition station includes an environmentally controlled processing enclosure, a first processing station configured to clean and activate a surface of a substrate, a second processing station configured to electrolessly deposit a layer onto the surface of the substrate, and a substrate transfer shuttle positioned to transfer substrates between the first and second processing stations. The system also includes a substrate transfer robot positioned on the mainframe and configured to access an interior of the processing enclosure. The system also includes a substrate a fluid delivery system that is configured to deliver a processing fluid by use of a spraying process to a substrate mounted in the processing enclosure.
Owner:APPLIED MATERIALS INC
Copper technology for ULSI metallization
InactiveUS6919266B2Reduce diffuseFew process stepsSemiconductor/solid-state device detailsSolid-state devicesTungsten nitrideElectroless deposition
A copper damascene structure formed by direct patterning of a low-dielectric constant material is disclosed. The copper damascene structure includes a tungsten nitride barrier layer formed by atomic layer deposition using sequential deposition reactions. Copper is selectively deposited by a CVD process and / or by an electroless deposition technique.
Owner:MICRON TECH INC
Activation-free electroless solution for deposition of cobalt and method for deposition of cobalt capping/passivation layer on copper
InactiveUS6902605B2Increase resistanceImprove barrier propertiesLiquid surface applicatorsSemiconductor/solid-state device manufacturingHigh resistanceElectroless deposition
The present invention relates to compositions and a method for electroless formation of alkaline-metal-free coatings on the basis of cobalt and composition of cobalt with tungsten and phosphorus, which have high resistance to oxidation and stability of electrical characteristics, when the Co—Cu system layer is used in IC chips. The composition of the electroless solution contains more than one reducing agents, one of which can catalyze the initial electroless deposition layer of cobalt on copper (called initiator), while the other maintains deposition of cobalt on the aforementioned initial layer as the process is continued. Small amount (100-5000 ppm) of elements from the initiator also builds into the electroless film, which is expected to further improve the barrier properties of the resultant film compared to the deposition bath without initiator. Such coating may find application in semiconductor manufacturing where properties of deposited films and controllability of the composition and physical and chemical characteristics of the deposited films may be critically important.
Owner:LAM RES CORP
Method and apparatus for selectively changing thin film composition during electroless deposition in a single chamber
Owner:APPLIED MATERIALS INC
Electroless deposition methods and systems
InactiveUS20050006339A1Simple and inexpensive methodAntibacterial agentsPretreated surfacesElectroless depositionActive layer
Methods and systems for depositing metal patterns on a substrate are provided. Accordingly, an electroless active layer can be formed on a substrate. Ink-jet techniques can then be used to independently ink-jet at least two components of an electroless deposition composition onto a variety of substrates. A metal composition can be ink-jetted onto the electroless active layer. The metal composition can contain a metal salt and optional additives. A reducing agent composition can be ink-jetted either subsequent to or prior to ink-jetting of the metal composition to form an electroless composition on the substrate. The metal salt and reducing agent react to form a metal pattern which can be used in formation of electronic devices or other products. The described ink-jettable compositions are stable over a wide range of conditions and allow for wide latitude in inkjet formulations and choice of substrates.
Owner:HEWLETT PACKARD DEV CO LP
Contact Layers For Thin Film Solar Cells Employing Group IBIIIAVIA Compound Absorbers
InactiveUS20070145507A1Semiconductor/solid-state device manufacturingPhotovoltaic energy generationCompound (substance)Engineering
The present invention provides methods and apparatus for deposition of contact layers for Group IBIIIAVIA solar cells using electrodeposition and / or electroless deposition approaches, and solar cells that result therefrom. In one aspect of the invention, the solar cell that results includes a substrate, a stacked contact layer that includes a bottom film coated on a surface of the substrate and a top film formed by electroplating over the bottom film, wherein the top film comprises at least one of Ru, Ir and Os. A Group IBIIIAVIA compound film formed over the top film. In another aspect of the invention, there is provided a method of depositing a stacked layer of a plurality of films in a plurality of sequentially disposed depositing units onto a continuously moving roll-to-roll sheet, preferably using electroplating of a stacked contact layer.
Owner:SOLOPOWER
Apparatus for electroless deposition
ActiveUS20050081785A1Liquid surface applicatorsVacuum evaporation coatingEngineeringElectroless deposition
Embodiments of the invention generally provide a fluid processing platform. The platform includes a mainframe having a substrate transfer robot, at least one substrate cleaning cell on the mainframe, and at least one processing enclosure. The processing enclosure includes a gas supply positioned in fluid communication with an interior of the processing enclosure, a first fluid processing cell positioned in the enclosure, a first substrate head assembly positioned to support a substrate for processing in the first fluid processing cell, a second fluid processing cell positioned in the enclosure, a second head assembly positioned to support a substrate for processing in the second fluid processing cell, and a substrate shuttle positioned between the first and second fluid processing cells and being configured to transfer substrates between the fluid processing cells and the mainframe robot.
Owner:APPLIED MATERIALS INC
Who we serve
- R&D Engineer
- R&D Manager
- IP Professional
Why Patsnap Eureka
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com