Electroless deposition apparatus

Abstract

An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of co-pending U.S. patent application Ser. No. 10 / 059,572, filed Jan. 28, 2002 and entitled “Electroless Deposition Apparatus.” This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 10 / 630,185, filed Jul. 29, 2003 and entitled “Electro-Chemical Deposition Cell For Face-Up Processing Of Single Semiconductor Substrates.” Each of the aforementioned related patent applications is herein incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to an apparatus and method of depositing a conductive material over sub-micron apertures formed on a substrate. [0004] 2. Description of the Related Art [0005] Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconducto...

AI Technical Summary

Problems solved by technology

However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities.

Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 2:1, and particularly where the aspect ratio exceeds 4:1.

Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free, sub-micron features having high aspect ratios.

As feature sizes decrease, the ability to deposit conformal seed layers can be compromised.

A discontinuous seed layer over the substrate may cause a number of problems during electroplating.

Particularly with physical vapor deposition of a seed layer, it is very difficult to deposit a continuous, uniform seed layer within a high aspect ratio, sub-micron feature.

The seed layer tends to become discontinuous especially at the bottom surface of the feature because it is difficult to deposit material through the narrow (i.e., sub-micron) aperture of the feature.

Discontinuities in the metal seed layer may cause void formations in high aspect ratio interconnect features.

The void changes the operating characteristics of the interconnect feature and may cause improper operation and premature breakdown of the device.

One problem with the disclosed process is that providing an “enhanced seed layer” depends on an electroplating process over a copper seed layer which may exhibit the problems discussed above.

Particularly with physical vapor deposition of a seed layer, it is very difficult to deposit a continuous, uniform seed layer within a high aspect ratio, sub-micron feature.

The seed layer tends to become discontinuous especially at the bottom surface of the feature because it is difficult to deposit material through the narrow (i.e., sub-micron) aperture of the feature.

Discontinuities in the metal seed layer may cause void formations in high aspect ratio interconnect features.

The void changes the operating characteristics of the interconnect feature and may cause improper operation and premature breakdown of the device.

One problem with the disclosed process is that providing an “enhanced seed layer” depends on an electroplating process over a copper seed layer which may exhibit the problems discussed above.

The patent, however, does not disclose the processing conditions for the electroless deposition of the materials over sub-micron features.

Barrier layers comprising titanium, titanium nitride, tantalum, and tantalum nitride are poor surfaces for nucleation of a subsequently deposited conductive material layer since native oxides of these barrier layer materials are easily formed.

However, where there are discontinuities in the seed layer, nucleation of a subsequently deposited conductive material layer is incomplete and may not form uniformly over the seed layer.

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