High-reliability chip scale packaging method

Abstract

The invention discloses a high-reliability chip scale packaging method. The method comprises the following steps: forming a heat-resisting metal layer and a metal wetting layer sequentially on a welding pad and a passivation layer on a chip; forming a photoresist on the metal wetting layer, wherein the photoresist is provided with the metal wetting layer with an opening exposed above the welding pad of the chip; forming a blocking layer and a welding flux protection layer sequentially on the metal wetting layer in the opening; removing the photoresist; etching the heat-resisting metal layer and the metal wetting layer which are positioned on the passivation layer until the passivation layer is uncovered; forming a protection adhesive layer on the chip, wherein the welding flux protection layer is covered by a protection adhesive; exposing the protection adhesive above a connection layer so as to form an opening, and uncovering the upper surface of the welding flux protection layer; and forming a welding flux bump on the welding flux protection layer and reflowing. According to the invention, the electric property and reliability of products are improved.

Description

technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to a metal layer under a solder bump and a method for forming a wafer level chip scale package (Wafer Level chip Scale Package, WLCSP). Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in th...

AI Technical Summary

Problems solved by technology

[0012] In the process of forming wafer-level chip size packaging in the prior art, since the solder bump material is in direct contact with the metal wetting layer, the copper in the metal wetting layer easily diffuses into the tin of the solder bump to form a copper-tin alloy, which affects the welding quality

At the same time, before the solder is formed on the metal wetting layer, the exposed wetting layer is easily oxidized, which reduces the performance and reliability of the subsequently formed solder bumps

On the other hand, during the formation of solder bumps, the solder is easy to drip and affect the reliability of the product, especially for products with dense metal pads, the problem of short circuit between solder bumps is more likely to occur

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