A method for forming solder bumps

A solder bump and solder paste technology, which is applied in the field of semiconductor device packaging, can solve the problems of affecting soldering quality, solder bump performance and reliability reduction, etc., and achieve the effect of increasing the number of functional output ports and meeting the fine pitch

Active Publication Date: 2016-02-03
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the process of forming wafer-level chip size packaging in the prior art, since the solder bump material is directly in contact with the metal wetting layer, the copper in the metal wetting layer easily diffuses into the tin of the solder bump to form a copper-tin alloy, which affects the soldering quality
At the same time, before the solder is formed on the metal wetting layer, the exposed wetting layer is easily oxidized, which reduces the performance and reliability of the subsequently formed solder bumps

Method used

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  • A method for forming solder bumps
  • A method for forming solder bumps
  • A method for forming solder bumps

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Embodiment Construction

[0023] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] figure 2 It is a flowchart of a specific implementation manner of forming solder bumps of the present invention, including the steps:

[0025] S101, forming a heat-resistant metal layer and a metal infiltration layer in sequence on the pad and the passivation layer of the chip;

[0026] S102, forming a photoresist on the metal infiltration layer, the photoresist is provided with openings to expose the metal infiltration layer above the chip pad;

[0027] S103, sequentially forming an adhesion layer and a barrier layer on the metal infiltration layer in the opening;

[0028] S104, forming a solder paste on the barrier layer;

[0029] S105, removing the photoresist;

[0030] S106, etching the heat-resistant metal layer and the metal infiltration layer on the passivation layer until the passivation layer is exposed;

[0031] S107, reflow the solder ...

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Abstract

The invention provides a method for forming a solder bump. The method comprises the following steps of: forming a heat resistant metal layer and a metal wetting layer on a pad and a passivation layer of a chip in sequence; forming a photoresist on the metal wetting layer, wherein the photoresist is provided with an opening to expose the metal wetting layer above the pad of the chip; forming an adhesion layer and a barrier layer on the metal wetting layer in the opening in sequence; forming solder paste on the barrier layer; removing the photoresist; etching the heat resistant metal layer and the metal wetting layer on the passivation layer until the passivation layer is exposed; and ensuring the solder paste to reflow to form a pillar bump. The method has the effect of improving the electrical property and reliability of the solder bump and is suitable for chip scale package with the requirements of fine pad pitch and multiple output functions.

Description

Technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to a method for forming flip-chip soldering, solder bumps, and wafer level chip scale package (Wafer Level chip Scale Package, WLCSP). Background technique [0002] In recent years, as the microcircuit production of chips has developed towards high integration, its chip packaging also needs to develop in the direction of high power, high density, lightness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of chip packaging are power transmission (PowerDistribution), signal transmission (SignalDistribution), heat dissipation (HeatDissipation) and protection and support (Protection and Support). [0003] Since the requirements of today's electronic products are light, thin, short, small and highly integrated, it wi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48
CPCH01L24/11H01L2224/11H01L2924/14H01L2924/00H01L2924/00012
Inventor 石磊
Owner NANTONG FUJITSU MICROELECTRONICS
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