Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit

一种干法刻蚀、氮化硅的技术,应用在电路、电气元件、半导体/固态器件制造等方向,能够解决栅条宽度不能自对准形成、没有形成三栅结构等问题,达到避免栅材料残留、刻蚀量小、避免电学等效厚度增加的效果
CN102646599AActive Publication Date: 2012-08-22PEKING UNIV

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV
Publication Date
2012-08-22

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Abstract

The invention discloses a preparation method of a FinFET (Fin Field Effect Transistor) in a large-scale integration circuit. The method disclosed by the invention is a rear gate process and comprises the following steps of: carrying out primary pseudo gate photoetching and etching on a plane by utilizing STI (Shallow Trench Isolation) chemical-mechanical polishing; forming a source drain; depositing an intermediate medium layer; grinding the intermediate medium layer to reach the top of the primary pseudo gate by utilizing chemical-mechanical polishing again; removing the pseudo gate by utilizing a dry etching and wet etching combination method; re-etching an STI medium by utilizing a hard mask formed by the intermediate medium layer, thereby forming a Fin structure only on the area of a gate electrode; and finally carrying out real gate medium and gate electrode material deposition, thereby obtaining a final device structure. The method disclosed by the invention can be used for obtaining a flat gate line photoetching plane, and simultaneously avoiding the problem of gate material residues on a Fin sidewall, and in addition, the method disclosed by the invention can be used for effectively integrating a high-K metal gate process, avoiding increase in electric equivalent thickness and shift of a work function, thereby obtaining excellent device characteristics.
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Description

technical field

[0001] The invention belongs to the technical field of large-scale semiconductor integrated circuit manufacturing, and relates to a process integration scheme for large-scale integrated circuit devices. Background technique

[0002] As Moore's Law advances to the 22nm technology node, the traditional planar field effect transistor can no longer meet the requirements of low power consumption and high performance. In order to overcome the short-channel effect and increase the driving current density per unit area, three-dimensional fin field-effect transistors (FinFETs) began to be introduced into large-scale integrated circuit manufacturing technology. This structure has a very prominent short channel control force and high drive current due to more gate control area and narrower channel depletion region.

[0003] The difficulty in process preparation of FinFET is the main reason that limits its application in large-scale integrated circuit products. One of ...

Claims

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