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Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve the problems of low yield of semiconductor devices and the gate cannot meet the threshold voltage, so as to prevent boundary movement and improve yield. Effect

Pending Publication Date: 2022-07-05
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0003] However, in the semiconductor device obtained by the existing manufacturing method, the gate of the first gate-all-round transistor or the second gate-all-around transistor cannot meet the corresponding threshold voltage requirements, resulting in a low yield rate of the semiconductor device

Method used

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  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device

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Embodiment Construction

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions / la...

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Abstract

The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and aims to prevent a first grid electrode on a corresponding second region from being damaged when the first grid electrode on a corresponding first region is removed. The manufacturing method of the semiconductor device comprises the steps of forming at least one layer of first nanowires or sheets on a first region of a substrate, and forming at least one layer of second nanowires or sheets on a second region of the substrate. And forming a first mask layer and a second mask layer. The first mask layer is at least filled in the gap. The second mask layer covers the second area. The etching selection ratio of the first mask layer to the second mask layer is greater than a preset threshold value. And under the masking effect of the second mask layer, removing the part, corresponding to the first region, of the first mask layer, and removing the first grid electrode corresponding to the first region. And at least forming a second gate on the first gate dielectric layer on the periphery of the at least one layer of first nanowire or sheet, wherein the second gate and the first gate contain different materials and / or different thicknesses.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor device. Background technique [0002] In the actual manufacturing process of the semiconductor device, the first gate-all-around transistor is formed on the first region of the semiconductor device. A second gate-all-around transistor is formed on the second region of the semiconductor device. In order to make the two gate-all-around transistors have different threshold voltages, a common method is to set the gates of the two gate-all-around transistors to different materials and / or different thicknesses. [0003] However, in the semiconductor device obtained by using the existing manufacturing method, the gate of the first gate-all-around transistor or the second gate-all-around transistor cannot meet the corresponding threshold voltage requirements, resulting in low yield of the semiconductor device. SUMMARY OF T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8234H01L27/088
CPCH01L21/823456H01L21/82345H01L21/823431H01L27/0886
Inventor 李永亮贾晓锋殷华湘罗军王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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