Method for preparing double side dielectric groove part SOI material

Abstract

The invention discloses a method for preparing double side dielectric groove part SOI material. Compared with the conventional bonding technology, before bonding, the method adds the following steps: 1. silicon groove etching on top layer silicon chip; 2. thermal growth and chemical vapor deposition of SiO2 layer; 3. removing the SiO2 layer positioned in a source area and under a channel region by etching; 4. deposition of polysilicon; 5. planarization of the polysilicon. As devices manufactured on the SOI material prepared by the method pass through reinforcing buried oxide layer electric field, the pressure resistance of the devices can be improved, and heat can be fully dispersed. Compared with devices with the conventional SOI structure, SOI devices prepared on the SOI material prepared by the method can utilize thinner top layer silicon and the buried oxide layer to reach the same pressure resistance, thus further reducing self-heating effect.

Description

technical field [0001] The invention proposes a method for preparing SOI material in a double-sided dielectric groove, which provides a substrate material for a power integrated circuit on the SOI material, especially a substrate material for a power device, and belongs to the technical field of semiconductor power devices and power integration. In particular, it relates to the technical field of material preparation of SOI power devices. Background technique [0002] SOI (Semiconductor On Insulator) technology has been widely concerned and applied because of its advantages of high speed, high integration, low power consumption, easy isolation, strong radiation resistance and no latch-up effect. The breakdown voltage of an SOI device is determined by the smaller of the lateral breakdown voltage and the vertical breakdown voltage. The lateral withstand voltage design of SOI high-voltage devices can follow the same junction termination technology and RESURF (REduced SURface F...

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Problems solved by technology

However, this structure does not completely solve the problem of low withstand voltage of SOI devices. This is because, first, the electric field of the buried oxide layer does not increase significantly, σ S =0, the electric field E of the buried oxide layer I ≈3E S ; Second, the thickness of the buried oxide layer is 20-100nm, and the thickness of the top silicon layer is 20-300nm. According to formulas (1) and (2), the withstand voltage of the device is lower than 100V

Third, the structure has no buried oxide layer only at the source end away from the channel region, and the substrate si...

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