35results about How to "Prevent charge leakage" patented technology

An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

This invention provides a new design and fabrication for a three-dimensional crossbar architecture embedding a sub-micron or nanometer sized hole (called a molehole) in each cross-region. Each molehole is an electrochemical cell consisting of two or more sectional surfaces separated by a non-conductor (e.g. a dialectric layer and solid electrolyte). When used in electrochemical molecular memory device (EMMD), the architecture provides unique features such as a nano-scale electroactive surface, no interaction between memory elements, and easier miniaturization and integration.

This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory density (e.g., 1015 bits / cm3), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices are intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.

Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

A thin film transistor array comprising a plurality of common lines for providing the storage capacitance of pixels is provided. In particular, each of the common lines comprises a plurality of branches. Wherein, the common line and the branches thereof, and the pixel electrode constitute the storage capacitor. The branches are disposed at pixels where the luminance quality is bad. Therefore, the storage capacitance of the pixels can be enhanced without altering the aperture ratio of the pixels. Accordingly, the performance of the liquid crystal display panel can be improved.

A pixel image sensor has a high shutter rejection ratio that prevents substrate charge leakage to a floating diffusion storage node of the pixel image sensor and prevents generation of photoelectrons within the floating diffusion storage node and storage node control transistor switches of the pixel image sensor. The pixel image sensor that prevents substrate charge leakage of photoelectrons from pixel image sensor adjacent to the pixel image sensor. The pixel image sensor is fabricated on a substrate with an isolation barrier and a carrier conduction well. The isolation barrier formed underneath the floating diffusion storage node allows effective isolation by draining away the stray carriers and preventing them from reaching the floating diffusion storage node. The carrier conduction well in combination with the deep N-well isolation barrier separates the pinned photodiode region from the deep N-well isolation barrier that is underneath the floating diffusion storage node.

One object is to propose a memory device in which a period in which data is held can be ensured and memory capacity per unit area can be increased. The memory device includes a memory element, a transistor including an oxide semiconductor in an active layer for control of accumulating, holding, and discharging charge in the memory element, and a capacitor connected to the memory element. At least one of a pair of electrodes of the capacitor has a light-blocking property. Further, the memory device includes a light-blocking conductive film or a light-blocking insulating film. The active layer is positioned between the electrode having a light-blocking property and the light-blocking conductive film or the light-blocking insulating film.

The invention provides an image forming apparatus and an image forming method, capable of providing an image with little deterioration, even in case the image contrast has to be adjusted not for the purpose of image adjustment, such as for reducing the toner consumption amount or for preventing the leak in the charging device.

This invention provides a procedure for growing oligomers via a stepwise process. The oligomers can include porphyrins, which have been previously shown to be attractive candidates for molecular-based information storage. The stepwise synthesis procedure requires no protecting groups, thus eliminating protection / deprotection reactions that add complexity to the process.

A method of increasing the cell retention capacity of a silicon nitride read-only-memory on a wafer. The method includes carrying out a baking process after performing the last plasma treatment of the wafer but before a wafer sort test.