66results about How to "Improve the mismatch" patented technology

The invention discloses an image registration and multi-resolution fusion-based panoramic image splicing method. An adaptive threshold of sequence images is subjected to binary processing and image contour information is extracted by utilizing a pixel neighborhood relationship; a similar region of an image contour structure is quickly estimated through a similarity measurement method for Hu momentinvariant features; and SIFT feature point extraction is performed in a similar region part of two original images. Moreover, feature point initial matching is performed by using a bidirectional K-nearest classification algorithm; mismatched points are screened by an RANSAC algorithm; and an affine transformation matrix among the images is estimated. In addition, in an image fusion aspect, brightness equalization and local color mapping processing is adopted. Then, through an improved Laplacian pyramid multi-resolution fusion algorithm, spliced images are fused to realize seamless splicing. According to the method, the image splicing time is shortened, the image splicing efficiency is improved, the similar region can be quickly located, the mismatch in splicing is effectively improved, and the image registration precision is improved.

A second-order intermodulation distortion (IMD2) compensating circuit that detects a variation of DC level of a voltage pair of a mixer load and adjusts the variation of the DC level of the voltage pair. The second-order intermodulation distortion compensating circuit also calibrates a mismatch of a mixer as well as a mismatch of the mixer load.

A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

The invention provides a circuit board impedance line compensation method and device. The circuit board impedance line compensation method includes the following steps that 202, the line width of each impedance line corresponding to each characteristic impedance value is calculated according to the characteristic impedance value of each impedance line of a circuit board, the dielectric thickness of the circuit board, the thickness of face copper and a dielectric constant; 204, the line width compensation value of each impedance line is obtained according to the thickness of the face copper of the circuit board and the calculated line width of each impedance line; 206, compensation is conducted on the impedance lines of the circuit board according to the obtained line width compensation value of each impedance line. According to the circuit board impedance line compensation method, the corresponding line width compensation values of all the impedance lines can be obtained at the same time, the circuit board compensation device can be used for fast conducting compensation on the line widths of all the impedance lines of the circuit board, and the production efficiency is improved effectively.

The invention discloses a DOA estimation method in a co-prime array based on iteration sparse reconstruction. A receiving antenna array uses a nonlinear co-prime array, through vectorized processing on a second-order statistical characteristic covariance matrix of a received signal, and a difference array in larger aperture length can be determined, so as to improve detection capability. Dispersing processing is performed on the angle domain where targets are in, targets can be regarded as sparsely distributed on grid points or near grid points, and sparse signal reconstruction problems on logarithm and forms are established. Using convex compact upper bounds of logarithm and a function, an original sparse problem is reestablished, to dynamically adjust and update discrete points of the angle domain in an iterative manner, so approach the actual arrival angle of the target.

A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.

A method for improving electromagnetic wave absorption performance of Fe-Si-Al powder relates to the technology of electromagnetic wave absorption and comprises the following steps: 1) performing ball mill flattening treatment on Fe-Si-Al soft magnetic alloy powder; 2) fast and mechanically stirring the powder obtained through the step 1) and scattering the powder into water and leading in air from the bottom of a container; 3) respectively preparing mixed salt solution with the corresponding molar ratio according to spinel ferrites to be wrapped, and preparing strong alkali solution according to the corresponding molar ratio; 4) stirring the scattered solution obtained by the step 2) under water bath heating at the temperature of 25-80 DEG C; 5) adding the salt solution and the strong alkali solution which are prepared through the step 3) into treated solution treated by the step 4); and 6) finishing reaction, cleaning the powder, drying and annealing. The method for improving the electromagnetic wave absorption performance of the Fe-Si-Al powder greatly reduces dielectric constant and simultaneously improves the microwave magnetic conductance of the powder.

The invention discloses a C-SF-FA flexible conductive film based on silk fibroin and a monitoring sensor made of the C-SF-FA flexible conductive film. The C-SF-FA flexible conductive film is preparedby the following steps of: 1) degumming silk, dissolving the silk in a salt-formic acid system to obtain a silk fibroin solution, performing drying to obtain silk fibroin, soaking the silk fibroin indeionized water, and dissolving the dried silk fibroin in formic acid again to obtain an SF-FA electrospinning solution; 2) dissolving dopamine in water, and adding carbon nanotubes to obtain a DA-CNTsolution; (3) preparing the SF-FA electrospinning solution into a flexible film through electrospinning, and spraying the DA-CNT solution onto the film for multiple times in the electrospinning process; airing the film to obtain a C-SF-FA conductive film; and 4) adding DA and CNT into an alkaline solution to obtain a PDA-CNT solution, soaking the C-SF-FA conductive film in the PDA-CNT solution, performing cleaning and drying, conducting soaking in an ethanol or methanol solution, and performing drying.

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells enhanced by stress for increased PUF output reproducibility. Stress voltage applied to SRAM bit cells enhances their skew so that the SRAM bit cells output their preferred initial state in subsequent PUF read operations regardless of process variation and other external environmental variations, such as temperature. The application of stress voltage on the SRAM bit cells in a PUF memory array takes advantage of the recognition of aging effect in transistors, where turning transistors on and off over time can increase threshold voltage resulting in lower drive current. Stress voltage can be applied to the SRAM bit cells to bias their threshold voltage to simulate this aging effect to enhance mismatch between transistors in the SRAM bit cell to more fully skew the SRAM bit cells for increased PUF output reproducibility with less susceptible to noise.

The invention belongs to the field of manufacturing of powder metallurgy automobile parts, and in particular relates to a double-material powder-forging gear with high performance and low cost, and amanufacturing method thereof. The gear structure comprises a gear tooth part, a gear core part and a middle gradient layer, wherein the gear tooth part is Fe-based alloy containing alloy elements suchas Ni, Cr and Mo and with high hardness and high wear resistance; and the gear core part is Fe-C-Cu alloy with low cost. The interface is provided with alloy powder consisting of two kinds of powderaccording to a specific ratio and the alloy powder is added according to the gradient layer design mode. Through design and powder forging forming of three parts of materials such as the tooth part, the gradient layer and the core part, the production cost of the gear is reduced, the performance of the gear is improved, and the problem that the interfaces are not matched, for example, the interfaces are cracked, bended and deformed, which is caused by the component difference between the two sides of the double-material powder-forging gear is great is solved through design of the gradient layer.

The invention relates to a plastic package and a preparation method thereof. The plastic package comprises a chip 1, a supporting piece 2 used for supporting the chip and a packaging shell 5. The packaging shell 5 comprises a first plastic package layer 3 which coats the chip 1 so as to enable the chip 1 to be sealed and a second plastic package layer 4 which coats the first plastic package layer 3 so as to enable the first plastic package layer 3 to be sealed, wherein the first plastic package layer 3 is made of a first resin material; the second plastic package layer 4 is made of a second resin material; and an equivalent thermal expansion coefficient of the first resin material is less than an equivalent thermal expansion coefficient of the second resin material. The plastic package provided by the invention is wide in material selection range, and can reduce delamination and failure of products, thereby improving the reliability of the products.

The invention provides a heat storage type air source heat pump water cooling and heating system and an operation method thereof, and belongs to the field of heat pump technologies and refrigerating air conditioners. The system comprises an outdoor source side, a heat pump host, a user side and a heat storage module. The outdoor source side comprises a refrigerating medium pump, an air cooling heat exchanger and source side valves. An outlet of the refrigerating medium pump is sequentially connected with the air cooling heat exchanger and the source side valves through pipelines and then returns to an inlet of the refrigerating medium pump through a first liquid cooling type heat exchanger of the heat pump host. A heat storage side mainly comprises a first valve, a second valve, a heat storage box, a third valve and a fourth valve. One side of the heat storage box is sequentially connected with the first valve and the source side valves on the source side through pipelines and then returns to the heat storage box through the second valve. The other side of the heat storage box is sequentially connected with the third valve and the user side valve on the user side through pipelines and then returns to the heat storage box through the fourth valve. By adopting the heat storage type air source heat pump water cooling and heating system, the capacity of a heat pump system supplying heat in winter can be greatly reduced, the primary investment is lowered, and the operation efficiency of the heat pump is improved.

The invention relates to a method for preparing magnesium aluminate spinel monocrystal, wherein the structure of magnesium aluminate spinel monocrystal is MgO .(Al2O3)n; n=1.3, 1.5, 2.0, 2.3, 2.5, 2.7, 3.0, 3.5, 4.5, 5.0; and the preparation comprises: (1) based on selected n value, preparing relative MgO and Al2O3; (2) sintering raw materials in neutral gas; (3) in neutral gas, using middle-frequency sensitive heating monocrystal furnace to grow crystal via drawing method; selecting n value, the crystal will form different optical effect to be used; when n=3, the crystal grid dismatch between spinel and GaN is lower to be processed easily, to form high-quality GaN substrate.

The invention discloses a light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the field of semiconductor technology. The epitaxial wafer comprises a substrate and a buffer layer sequentially laminated on the substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the active layer comprises a plurality of composite structures laminated in sequence, each of the composite structures comprises a well layer, a cap layer and a barrier layer laminated in sequence, the material of the well layer is InGaN, the material of thebarrier layer is GaN, and the material of the cap layer is BxGa1-xN, 0<x<1. A lay of BGaN is inserted between InGaN and GaN, BGaN can provide tensile stress, improve lattice mismatch between InGaN and GaN, reduce piezoelectric polarization field caused by lattice mismatch between InGaN and GaN, and improve luminescence efficiency of LED because of small size of B atom.

The present invention discloses a method and an apparatus for modifying a channel quality indication (CQI). This method may comprise: calculating a scaling factor for the channel quality indication based on uplink channel information and an antenna virtualization pre-coding scheme; and modifying the channel quality indication reported by user equipment by using the scaling factor. According to the technical solutions of the present invention, the antenna virtualization factor is considered in performing CQI modification and. Thus, this solution can overcome the problem of CQI mismatch, enhance the completeness and accuracy of CQI feedback, and improve the cell throughput performance and frequency utilization.

The invention discloses an anti-sticking coating, a carbon-based boat and a preparation method thereof. The anti-sticking coating comprises a transition layer and a working layer, wherein the transition layer comprises chromium group elements, and the working layer is arranged on at least one part of the transition layer and comprises at least one of aluminum oxide, zirconium oxide and rare earthoxide. Therefore, the bonding strength between the anti-sticking coating and the boat can be improved, and the isolation capacity of the coating is enhanced. When the anti-sticking coating is appliedto the surface of the carbon-based boat for hard alloy sintering, the transition layer in the anti-sticking coating and a carbon-based boat base body have good bonding strength, mismatching of thermalexpansion coefficients between a carbon substrate and the working layer can be improved, the element mutual diffusion effect between the carbon-based boat base body- coating-hard alloy products is inhibited, and the thermal stability of the anti-sticking coating is improved, so that the phenomena of coating peeling and sintering deformation, carburization and decarburization of the hard alloy products caused by the fact that the hard alloy products are stuck to the surface of the boat can be avoided, and the service life of the anti-sticking coating is greatly prolonged.

The invention discloses an anti-corrosive anti-impact wearable steel ball. The anti-corrosive anti-impact wearable steel ball comprises, by weight, 0.7-0.75% of C, 11-13% of Cr, 1-1.2% of Si, 1.5-1.6% of Mn, 0.05-0.06% of B, 1-2% of Ni, 2.1-2.15% of Y, 0.04-0.06% of Ti, 0.03-0.05% of Cu, 0.01-0.03% of Co, 0.3-0.4% of Zr, 0.03-0.04% of Nb, less than or equal to 0.012% of P, less than or equal to 0.002% of S, and the balance Fe. The invention further discloses a preparation method of the anti-corrosive anti-impact wearable steel ball. The anti-corrosive anti-impact wearable steel ball is good in corrosion resistance, high in impact resistance and good in wear resistance.

The invention discloses a light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the field of semiconductor technology. The epitaxial wafer comprises a substrate and a buffer layer sequentially laminated on the substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the active layer comprises a plurality of composite structures laminated in sequence, each of the composite structures comprises a well layer, a cap layer and a barrier layer laminated in sequence, the material of the well layer is InGaN, the material of thebarrier layer is GaN, and the material of the cap layer is BxIn1-xN, 0<x<1. A lay of BInN is inserted between InGaN and GaN, The size of B atom is small, so BInN can compensate the stress effectively, realize the lattice matching with InGaN and GaN, improve the lattice mismatch between InGaN and GaN, reduce the piezoelectric polarization field caused by the lattice mismatch between InGaN and GaN,and improve the luminescence efficiency of LED.

A capacitor and a formation method thereof are disclosed. The capacitor comprises: a plurality of pseudo electrodes which are formed on a semiconductor basement and are arranged as an array; dielectric layers which are formed on surfaces of the pseudo electrodes and on a surface of the semiconductor basement; first electrodes and second electrodes which are formed on the dielectric layers, wherein insulation materials are filled between the first electrodes and the second electrodes. By using the invention, a mismatch problem of the capacitor can be improved.

The invention discloses a method of arrangement of a current cell and a curent cell array using such method. The curent cell array includes a number of current cell groups. Each of the current cell groups includes a number of current cells. In the method of arrangement of the current cell, firstly an initial current cell array is provided; then the current cells in the current cell array is divided into a plurality of current cell groups; a first identification code is assigned to each of the current cell groups and a second identification code is assigned to each of current cells, wherein the first and second identification codes are on the basis of a gradient of the initial current cell array; the current cells are arrayed based on the first and second identification codes to provide a layout of a final current cell array; sequently the layout of the final current cell array is in a computer readable memory medium.

The invention discloses a digital system for image rejection of a low-intermediate-frequency receiver and an implementation method thereof. The digital system comprises a direct-current calculation module, a first subtractor, a conjugated calculation module, a power calculation module, a self-adaptive filter calculation module and a plurality of band-pass filter modules; the direct-current calculation module is used for receiving I and Q data and outputting I0 and Q0 data; the first subtractor is used for receiving the I and Q data and the I0 and Q0 data so as to obtain I1 and Q1 data; the conjugated calculation module is used for receiving the I1 and Q1 data so as to obtain I2 and Q2 data; the power calculation module is used for receiving the I1 and Q1 data so as to obtain IQ-POW data; the self-adaptive filter calculation module is used for receiving the I1, Q1, I2, Q2 and IQ-POW data so as to obtain I4 and Q4 data; and the plurality of band-pass filter modules are used for receiving the I4 and Q4 data so as to obtain I5 and Q5 data. IQ mismatch can be improved obviously and stably although the digital system disclosed by the invention has a relatively simple structure.

This invention discloses one integration circuit capacitor structure, which comprises one dielectric layer and first, second and third wires, wherein, the dielectric layer is set on one underlay; first wire is imbedded into first level of dielectric layer; the second and third wires are imbedded into second level lower than first level with certain distance; the second wire is covered by one projection on underlay and the third wire is covered by one projection on underlay.

The invention discloses an anti-corrosive steel ball. The anti-corrosive steel ball comprises, by weight, 0.1-0.2% of C, 14-16% of Cr, 0.8-1.5% of Si, 1.5-2% of Mn, 0.02-0.03% of B, 0.5-1.5% of Ni, 0.05-0.07% of Cu, 1-2% of Y, 0-0.02% of P, 0-0.01% of S, and the balance Fe. The invention further discloses a preparation method of the anti-corrosive steel ball. The anti-corrosive steel ball is good in corrosion resistance, high in wear resistance and good in mechanical property.

The invention discloses a time-interleaved ADC mismatch optimization method based on task scheduling. The quantization time of a channel corresponding to a current quantization period is shortened orthe time length of the current quantization period is increased. The corresponding channel is quantified in advance to enter an idle state in the current quantization period. All the quantized channels are marked as idle channels, and then one channel from all the idle channels is randomly selected for sampling and quantization when the next quantization period comes by adopting a task schedulingalgorithm, so as to realize channel randomization to optimize inter-channel mismatch. According to the invention, the residual quantization time of the ADC of each channel is fully utilized, the purpose of random channels can be realized without additionally adding auxiliary channels, the spurious-free dynamic range of the time-interleaved ADC is improved, and the speed of the time-interleaved ADCand the adaptability under each condition are improved.

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The manufacturing method comprises the following steps: providing a semiconductor substrate; forming a diffusion barrier layer in the area that a gate structure is formed in a predetermined manner on the semiconductor substrate, wherein the diffusion barrier layer comprises metal and non-metal elements; and using plasma containing the non-metal elements to treat the dispersion barrier layer so as to reduce the content ratio of the metal elements to the non-metal elements inside the diffusionbarrier layer. According to the method provided by the invention, the distribution uniformity, on the semiconductor substrate, of the threshold voltage of the device can be improved, and the mismatching problem of local threshold voltage is solved so as to finally improve the performance and yield of the device.

The invention relates to the technical field of flip LED chips, and discloses a preparation method of a green light epitaxial structure. A substrate, a low-temperature AlGaN buffer layer, an N-AlGaN barrier layer, multi-period Si-doped GaN, a superlattice InGaN / GaN, a multi-period quantum well, a barrier layer, Mg-doped P-GaN and a contact layer are sequentially grown from bottom to top, and the multi-period quantum well adopts different In component structures of GaN / In<x1>Ga<1-x1>N / In<X>2Ga<1-x2>N / GaN. Therefore, through the quantum well segmented growth structure, well-barrier mismatch can be improved, the stark effect can be relieved, the luminous efficiency can be improved, and the growth yield can be improved.

The invention discloses a light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the field of semiconductor technology. The epitaxial wafer comprises a substrate and a buffer layer sequentially laminated on the substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the active layer comprises a plurality of composite structures laminated in sequence, each of the composite structures comprises a well layer, a cap layer and a barrier layer laminated in sequence, the material of the well layer is InGaN, the material of thebarrier layer is GaN, and the material of the cap layer is BxGa1-xN, 0<x<1. A lay of BGaN is inserted between InGaN and GaN, BGaN can provide tensile stress, improve lattice mismatch between InGaN and GaN, reduce piezoelectric polarization field caused by lattice mismatch between InGaN and GaN, and improve luminescence efficiency of LED because of small size of B atom.

The invention provides an inverter control method and system. The method is used for the inverter control process of a current inner-ring controller. The current inner-ring controller comprises an active current controller and a reactive current controller. The method comprises the steps that a k1-multiple output value of a voltage outer-ring controller is used as a reference value of the active current controller; a k2-multiple grid connection current active component is used as a feedback value of the active current controller; the ratio of the k2 to the k1 is a per unit value of the network voltage; according to the output value of the active current controller and the output value of the reactive current controller, a driving signal for the inverter is generated; the driving signal is output to the inverter to control an inverter to work. According to the inverter control method and system, the ratio of the k2 to the k1is the per unit value of the network voltage, so that the phenomenon that direct-current power output power is not matched with output power of the inverter is avoided, the fluctuation range of direct-current bus voltage is reduced, and the oscillation amplitude of the output current of the inverter is reduced.

The invention belongs to the technical field of integrated circuit design, and relates to a differential charge pump circuit with an operational amplifier. The differential charge pump circuit comprises a current source I1, a pull-up current mirror, a pull-down current mirror, a transmission gate switch, the operational amplifier, a first resistor R1, a first capacitor C1, a second capacitor C2, athird capacitor Cp3 and a fourth capacitor CP4. The differential charge pump circuit has the following beneficial effects that (1) the problem that the charging current and the discharging current ofa traditional charge pump are not matched is solved; ; (2) the problem of clock feed-through is solved; and (3) the charge sharing effect influence is improved.