302results about "Computer designed circuits" patented technology

The invention provides a new energy automobile control circuit board production process optimization control method and system, and relates to the technical field of production control, and the method comprises the steps: collecting production process parameters in real time, inputting the parameters into a process digital twin model, and obtaining process deviation data; and inputting the deviation data into a process parameter optimization model based on a deep reinforcement learning algorithm to generate an adjustment instruction, performing real-time parameter adjustment on the production line, and feeding back to a digital twinborn model to form closed-loop control. According to the invention, accurate monitoring and intelligent optimization of the production process can be realized, the production quality and the production efficiency of the circuit board are improved, and the rate of defective products is reduced.

The invention relates to the technical field of electromagnetic shielding compensation, and discloses an electromagnetic shielding compensation method and system for an FPC high-performance computing chip interface, and the method comprises the steps: carrying out the impedance signal collection of the FPC high-performance computing chip interface, obtaining a time domain signal and a second-order change rate curve, a time domain signal is acquired by applying an alternating current excitation signal between a signal layer and a grounding layer; performing feature extraction on the time domain signal and the second-order change rate curve to obtain a feature vector; inputting the feature vector into a support vector machine model to perform electromagnetic interference classification identification to obtain an electromagnetic interference mode type; performing weighted fusion analysis on the time domain signal to obtain an electromagnetic interference state parameter; according to the method, a layered compensation controller is constructed, the impedance parameters of the shielding layer are adjusted through a self-adaptive backstepping control algorithm, compensation control parameters are obtained, accurate adjustment of the impedance parameters of the shielding layer is achieved, and stability and effectiveness of electromagnetic shielding compensation are guaranteed.

The invention relates to the technical field of PCB processing, and discloses a multi-layer circuit board drilling method and device based on machine vision, and the method comprises the steps: obtaining a multi-layer circuit board image; preprocessing the multi-layer circuit board image to obtain a to-be-identified image; inputting the to-be-recognized image into a pre-trained defect detection model to obtain defect position data; carrying out point location identification and matching on the to-be-identified image to obtain an optimal hole location coordinate, and carrying out correction according to the optimal hole location coordinate to obtain hole location information data; according to the hole site information data and the defect position data, nodes are constructed respectively, distance calculation is carried out, and a hole site node graph is generated; according to the hole site node graph, performing path planning by applying an ant colony algorithm, and performing iterative search to obtain an optimal drilling path; and drilling the multilayer circuit board according to the optimal drilling path. The method has the following effect that the drilling efficiency of the multilayer circuit board can be improved.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

The invention relates to the technical field of circuit component layout, in particular to a component layout system of a DC-DC power module, which obtains a candidate position range according to a first preset position range and a second preset position range, and obtains a reference distance according to an initial value set, a target value, a preset wiring width and a preset dielectric constant. According to the method, a series of possible candidate positions are generated by comprehensively considering different distance and angle combinations, so that the layout possibility of a target element on a target printed circuit board can be comprehensively explored, and an output voltage sequence and response delay time corresponding to each candidate position are obtained respectively; according to the method, performance of stability, accuracy, reliability, timeliness and the like of a circuit under different candidate positions is represented through the characteristic of the candidate positions, then the target priority corresponding to each candidate position is obtained, the candidate position corresponding to the maximum target priority is determined as the target position of the target element, the layout reasonability of the target element is improved, and the reliability of the circuit is improved. And the performance and the reliability of the whole circuit are improved.

The invention provides an industrial circuit board intelligent repairing method and system based on a lossless damping chip, and the method comprises the steps: obtaining multi-dimensional acoustic response data in an industrial circuit board, carrying out the spatial analysis of a phase offset in the data, and generating a three-dimensional geometric boundary coordinate set of a microcrack region; activating a resonant wave stabilization processing mode of the lossless damping chip, and generating a mechanical resonant frequency and a dynamic constraint force field for inhibiting crack propagation; generating a target filling scheme according to the stress distribution state of the dynamic constraint force field; constructing a conductive filling path topological structure, and generating a continuous conductive interface; according to the resonance response characteristic between the continuous conductive interface and the mechanical resonance frequency, a micron-sized crack repairing scheme is generated, and intelligent repairing of the industrial circuit board is carried out. The method breaks through the problem of fuzzy positioning of the crack spatial form in the traditional detection technology; the accurate permeation of the filling material along the crack is ensured; verification and closed loop feedback of the repairing effect are achieved, and the stability and reliability of the repaired industrial circuit board are remarkably improved.

The invention discloses a circuit board X-shaped hole processing control method, system and device and a medium. The method comprises the following steps: acquiring a first image of a first surface blind hole after a preset depth h'is processed for the Nth time; acquiring first hole offset data according to the first image; according to the first hole offset data, first hole machining correction parameters are obtained so as to guide machining of the first face blind hole; acquiring a second image of the blind hole in the second surface after the preset depth h'is processed for the Nth time; acquiring second hole offset data according to the second image; according to the second hole offset data, second hole machining correction parameters are obtained so as to guide machining of a second face blind hole; the X-shaped hole detection method and device have the advantages that the hole machining quality can be effectively controlled, and the detection accuracy is high.

The invention discloses a graphic design method for balancing the copper thickness of an impedance line. The graphic design method comprises the following steps: S1, determining a first residual copper rate of a graphic area of an impedance strip layer on a circuit board; s2, acquiring a second residual copper rate of an impedance strip area of an impedance strip layer on the circuit board; s3, the absolute value m of the difference between the second residual copper rate and the first residual copper rate is calculated; s4, m is compared with 5%, and if m is larger than 5%, the step S41 is executed; if m is less than or equal to 5%, executing the step S42; s41, adjusting the width of the auxiliary copper sheet on the two sides of the impedance line in the impedance strip area, and returning to execute the step S2, the step S3 and the step S4 after the adjustment is completed until m is less than or equal to 5%; and S42, simulating a circuit of the pattern area on the auxiliary copper sheet to carry out dummy impedance line distribution in the impedance strip. According to the method, the difference between the copper plating thickness of the impedance strip coupon impedance line of an FCBGA product and the copper plating thickness of an actual graphic circuit can be reduced, and it is guaranteed that the impedance value simulated by the coupon impedance line of the impedance strip has reference significance.

The invention relates to the technical field of circuit board processing, and discloses a circuit board back drilling stub control method, device and equipment and a medium, and the circuit board back drilling stub control method comprises the steps: carrying out the board thickness measurement of a circuit board, obtaining the original board thickness data, carrying out the difference analysis, and carrying out the piling and measurement processing according to the analysis result; obtaining a plate thickness data set corresponding to each pile; measuring and analyzing the target back drilling hole position to obtain grouped plate thickness data, calculating the influence degree of the plate thickness on the length of the back drilling stub, comparing the influence degree with a preset threshold value, and judging a back drilling depth adjusting scheme; and according to a judgment result, back drilling processing depth parameters of the whole or the partitions are calculated, and differentiated depth optimization control is achieved. According to the method, the stub range can be effectively reduced in multi-batch and high-layer PCB machining, the back drilling depth control precision is improved, and it is ensured that the stub length is stable and meets the high-specification signal integrity requirement.

The invention relates to the technical field of element bonding pad matching, in particular to a method for automatically matching a component and a bonding pad, which comprises the following steps of: directly and dynamically calculating a coverage area according to the size of the component, and detecting a bonding pad layer in real time without pre-storing a mapping relation; the electrical feasibility verification that the number of bonding pads is greater than or equal to the number of pins is increased to solve the risk of insufficient solder or solder skips; the coordinate correction is matched with the mean correction coordinate of the central point of the bonding pad, and the angle correction is realized by identifying a silk-screen polarity identifier through AI to realize a dual-stage correction technology; polarity identification consistency verification is newly added, so that the installation correctness of a high-reliability device is ensured, and polarity direction guarantee is realized; the workload of a client for pre-storing the template is reduced, and the matching precision is improved through dynamic detection and closed-loop correction.

The invention discloses a multilayer circuit board preparation method and system based on via hole filling optimization and a multilayer circuit board, and relates to the technical field of circuit board preparation, and the method comprises the steps: obtaining the size of a via hole, calculating the depth-to-width ratio, constructing a viscosity gradient function, taking a via hole filling quality evaluation index as a first optimization target, and solving an optimal ratio; designing a vacuum degree control strategy; the current capillary pressure is obtained, differential pressure driving force is calculated according to the current through hole gas pressure intensity, the time needed for filling and the preset ultrasonic vibration duration are calculated in combination with the through hole diameter, the hole depth and the viscosity gradient function, and ultrasonic auxiliary filling is carried out while through hole filling is carried out; filling the via hole, and controlling the vacuum degree according to the vacuum degree adjusting curve; and the real-time filling rate and the cavity volume are obtained, a second target function is constructed with the difference between the minimum target filling rate and the actual filling rate and the filling cost as a second optimization target, and the optimal filling step number and the optimal single injection material volume are solved.

The invention discloses a design method of an inner-layer circuit board. The design method comprises the following steps: optimizing the design of the minimum distance from a hole to copper; hole ring design: a welding ring is greater than or equal to 4mil before compensation of a copper thick circuit of 1oz and below, local cutting is performed at least 3.5 mil after compensation, and teardrop design is added to all inner-layer circuit hole rings; wire design: the wire width of the functional connection wire is greater than or equal to the finished product wire width of the minimum bottom copper design; designing a non-functional bonding pad, wherein a single-side welding ring is greater than or equal to 8mil, and a slotted hole is greater than or equal to 10mil; fine gaps are designed, wherein non-functional fine gaps smaller than or equal to 5 mil are subjected to copper filling treatment; the gaps with the isolated copper spacing smaller than 10 mil are filled with copper; a heat dissipation welding ring is larger than or equal to 6 mil, a heat dissipation copper bridge is larger than or equal to 6 mil, and a copper bridge base material ring finished product is larger than or equal to 5 mil; when the heat dissipation pad intersects the isolation pad, the integrity of the isolation pad is preferentially satisfied. According to the design method of the inner-layer circuit board provided by the invention, the long-term reliability of the circuit board can be improved.

The invention discloses a primary impedance qualification design method for a PCB (Printed Circuit Board) process, which comprises the following steps of: measuring a medium thickness gradient, slicing a sample on a laminated PCB, measuring the thickness of a medium layer at each point by adopting a metallographic microscope, recording a board edge region, importing measured data into CAM (Computer Aided Manufacturing) software to generate a medium thickness distribution cloud picture, and dividing a compensation region; surface copper is measured, a thickness gauge is used for measuring the thickness of copper on the plate edge and in the plate after the ceramic plate is ground, and a comparison table of the copper thickness difference value and the line width deviation is established; compensation area division: dividing a board edge area, a transition area and an in-board area on the surface of the PCB by laser engraving; length compensation is carried out, 0.1 mi and 0.3 mi of medium thickness compensation and copper thickness compensation are carried out on the plate edge area, 0.05 mi and 0.15 mi of medium thickness compensation and copper thickness compensation are carried out on the transition area, and the total compensation amount of the plate edge area and the total compensation amount of the transition area are kept to be 0.4 mi and 0.2 mi respectively. The problems that in the prior art, a traditional PCB uniformization compensation design cannot adapt to regional process differences in actual production and multi-impedance-line cooperative regulation and control cannot be achieved are solved.

The invention relates to the technical field of positioning optimization, and discloses an electronic component pin PCB hole positioning optimization method, which comprises the steps of data acquisition, feature extraction, deviation analysis and optimization adjustment. High-precision optical measurement equipment is used for collecting data, coordinates of the pins and plate holes are accurately marked, the position and direction differences of the pins and the plate holes are accurately mastered through strict feature extraction and deviation analysis, and it is ensured that the pins are accurately inserted into the plate holes; the regular and irregular arrangement of the plate holes is fully considered, corresponding strategies are respectively formulated, and both complex precise electronic products and multi-sample plate hole design can be effectively adapted; according to calculation results of the center deviation and the angle deviation, the positions and directions of the pins are perfectly matched with the plate holes through translation and rotation adjustment, and the assembly reliability is guaranteed; the whole process is based on data quantification operation, subjective judgment uncertainty is avoided, operation normalization is improved, and powerful support is provided for development of the modern electronic industry.

The invention discloses a high-precision circuit board wet film processing method and system, and relates to the field of circuit board wet film processing, and the method comprises the complete manufacturing process of substrate pretreatment, wet film coating, LDI exposure, development, micropore etching and final film stripping. The key point is that a data barrier in a traditional process is broken through between LDI exposure and a downstream etching process. Specifically, key parameters of etching liquid are collected in real time in the etching stage, and an intelligent model capable of predicting the etching influence is constructed and continuously optimized in combination with an actual line width detection result of an etched plate. The model can be used for prospectively calculating an accurate dynamic etching compensation value according to the current state of the etching liquid, and feeding back the accurate dynamic etching compensation value to LDI equipment for adjusting the exposure line width. Therefore, the problem of compensation failure caused by etching liquid aging can be effectively solved, and the high consistency and stability of line width in cross-batch production are ensured.

The invention provides a neck copper area processing method and device in EDA design, equipment and a medium. The method comprises the steps that S110, an avoided copper sheet is obtained; s120, whether a neck copper area with the width smaller than a preset narrowest distance exists in the avoided copper sheet or not is recognized; and S130, if the neck copper area exists, cutting the neck copper area in the avoided copper sheet to obtain a cut copper sheet. According to the method, the ultra-fine area of the copper sheet after avoidance is identified through external expansion and intersection point solving of the convex polygon, the neck copper area is screened out by combining certain design detail requirements, and then the neck copper area is cut off through an operation function of the polygon with the hole, so that the quality and the efficiency of a circuit are ensured.

The invention discloses a printed circuit board element placement method and device based on a traveling salesman problem and a medium, belongs to the technical field of traveling salesman problems and printed circuit boards, and aims to solve the technical problem that diversified constraint conditions and efficiency are difficult to consider when the placement sequence of traditional printed circuit board elements is optimized. According to the technical scheme, the method comprises the following steps: constructing a training data set; performing feature coding on the placement requirement of the printed circuit board element by using an encoder to obtain a coding result; decoding a coding result through a decoder based on a double-pointer network, and generating an element placement sequence meeting the priority constraint; and training the encoder-decoder architecture by adopting a near-end strategy optimization algorithm based on reinforcement learning, and finally obtaining a deep reinforcement learning model for solving the priority constraint traveling salesman problem for placing the printed circuit board element.

The invention discloses an obstacle-avoiding wiring method, and relates to the technical field of printed circuit boards. The method comprises the following steps: acquiring a to-be-connected first endpoint and a to-be-connected second endpoint; connecting the first end point and the second end point by a straight line segment, and determining whether the straight line segment passes through the obstacle area; in response to the straight line segment passing through the obstacle area, obtaining an obstacle area contour corresponding to the obstacle area; and determining a connecting line between the first end point and the second end point according to the intersection point of the straight line segment and the obstacle area contour and the vertex of the obstacle area contour. By implementing the obstacle-avoiding wiring method, the obstacle-avoiding wiring device, the obstacle-avoiding wiring equipment and the circuit board wiring method provided by the invention, the generated wiring can effectively avoid the obstacle area on the circuit board.

The invention discloses a PCB layout design method and system based on heat dissipation optimization, and the method comprises the steps: carrying out the logic design and electrical performance analysis of a to-be-optimized PCB, and obtaining a preliminarily optimized PCB; performing simulation analysis on the preliminarily optimized PCB to obtain an optimization analysis result of the PCB; performing wiring optimization and multilayer board optimization on the preliminarily optimized PCB according to an optimization analysis result of the PCB to obtain an optimized PCB; and performing verification analysis on the optimized PCB according to an electrical design rule to obtain a final optimized PCB. According to the embodiment of the invention, the electromagnetic interference can be reduced, the electromagnetic compatibility and the heat dissipation capability of the circuit are improved, and the stable transmission of signals is realized. The method can be widely applied to the technical field of electronic circuit layout design.

The invention discloses an intelligent dynamic control method and system for a V-CUT machining process, and the method comprises the steps: arranging a multispectral laser displacement sensor array at a V-CUT cutter shaft, arranging a high-frequency piezoelectric micro-touch probe at a residual thickness measurement station, and generating point cloud data in real time based on a preset sampling frequency; synchronously mapping the point cloud data into a digital twin model corresponding to the V-CUT equipment, and updating the V-CUT groove depth, the PCB residual thickness and the V-CUT knife edge wear degree corresponding to the twin model in real time; predicting a cutter shaft machining drifting trend according to the groove depth, the residual thickness and the cutter edge abrasion state; and when the drift trend predicted value exceeds the process threshold value, a feed-forward compensation instruction is issued to a cutter shaft servo system, and closed-loop correction in the V-CUT machining process is achieved. According to the invention, production and detection integration can be realized, individual manual detection by personnel after shutdown is not needed, and quality improvement and production efficiency maximization can be effectively ensured.

The embodiment of the invention relates to an electronic design automation data checking method and electronic equipment. The method comprises the steps that to-be-checked electronic design automation data and a checking configuration file are obtained respectively; the checking configuration file comprises checking rules for checking the electronic design automation data, and the checking rules are editable rules; the check rule is structured data, and the structured data comprises a rule check function; and checking the to-be-checked electronic design automation data based on the rule checking function to generate a checking result. The checking configuration file is an editable rule, so that the checking rule for checking the electronic design automation data to be checked can be determined based on the editing operation of the user, and the checking rule in the configuration file can be flexibly adjusted according to the requirement of the user; according to the embodiment of the invention, the situation that the inspection content is relatively single and does not have expansibility in related technologies can be avoided, so that the inspection efficiency of the electronic design automation data can be improved.

The invention provides a method for controlling a soldering process, the method comprising the following steps: f) reading in CAD data regarding a circuit board on which electronic components are to be soldered to through-holes and / or pad fields, and using said CAD data as a circuit board model, the through-holes and / or pad fields each defining a soldering point, g) dividing the circuit board model into a plurality of circuit board segments, each circuit board segment having only a few soldering points, h) determining, for each individual circuit board segment, the distribution of an electrically conductive material contained in the circuit board segment, once in the plan view and once in a side view, so that a horizontal distribution and a vertical distribution are obtained, i) determining a minimum value and / or maximum value of at least one control parameter for a soldering process for soldering the soldering points, such that at least one predefined quality parameter is satisfied for all soldering points, the horizontal distribution and the vertical distribution of each segment being taken into account for this purpose, j) carrying out a soldering process, the at least one control parameter satisfying the determined minimum value and / or maximum value.

The invention discloses a multilayer printed circuit board wiring process, and relates to the technical field of electronic circuit board manufacturing, and the method comprises the steps: obtaining a wiring target and preset parameter conditions of a multilayer printed circuit board; calculating a target connection mode by adopting a circuit board wiring model based on the wiring target of the multi-layer printed circuit board and preset parameter conditions; coating photoresist on an inner-layer copper foil of the middle-layer substrate, transferring a circuit pattern to the copper foil through exposure and development processes according to a wiring target path, target layer selection, a target via hole position and a target element position, and drilling at a specified position by using a drilling machine; forming a conductive layer on the hole wall of the hole through an electroplating process; and repeating the manufacturing process of the inner layer of the middle-layer substrate on the outer-layer copper foil of the middle-layer substrate according to the wiring target path, the target layer selection, the target via hole position and the target element position to form an outer-layer circuit pattern. The efficiency of the wiring process of the printed circuit board is improved.

The invention discloses a parameter optimization method based on PCB processing abnormity identification, and relates to the technical field of circuit boards, and the method comprises the steps: obtaining the etching parameters of a PCB; determining the line width of the PCB; forming a copper residue short circuit discrimination mechanism; constructing an optimization model of the etching parameters; judging whether the etching of the PCB is abnormal or not; when parameters are optimized, positions where etching is abnormal are divided into a first abnormal position and a second abnormal position; and forming a first parameter optimization scheme at the first abnormal position, and forming a second parameter optimization scheme at the second abnormal position. By determining the line width of the PCB, forming a short-circuit discrimination mechanism of copper residues, constructing an optimization model of etching parameters, forming a first parameter optimization scheme and a second parameter optimization scheme, etching abnormalities at different positions in the circuit board are identified, and the etching duration of the positions with abnormalities is adjusted.

The invention provides a multilayer circuit board, a via hole structure optimization method and electronic equipment, and can be applied to the technical field of electronic equipment. The multilayer circuit board comprises a plurality of signal layers; the at least one first differential via hole structure is drilled in the multi-layer circuit board along a direction deviating from the normal direction of the multi-layer circuit board by a first drilling angle, so that at least two signal layers in the multiple signal layers in the multi-layer circuit board are electrically connected with each other; the at least one second differential via hole structure is drilled in the multi-layer circuit board in the direction deviating by a second drilling angle relative to the normal direction of the multi-layer circuit board, so that at least two signal layers in the multiple signal layers are electrically connected with each other; wherein the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via hole structure and the at least one second differential via hole structure intersect with each other.

The invention belongs to the technical field of electronic manufacturing and printed circuit boards, and particularly relates to a lamination method and system of a multilayer flexible circuit board, which comprises the steps of providing a flexible substrate layer, forming a graphical photosensitive layer, arranging a binder layer, stacking a multilayer structure, performing exposure development and lamination treatment and the like. The system comprises a material supply unit, a graphical photosensitive layer forming unit, a lamination stacking unit, a graphical processing unit and a lamination unit, and full-process automation is realized through a central control unit. According to the invention, the positioning and alignment precision can be improved, the material compatibility is optimized, the process integration level is enhanced, and the lamination quality is improved, so that the production efficiency and the product yield of the multi-layer flexible circuit board are remarkably improved.

A computer-implemented method for evaluating a minimum clearance distance between a first conductive element and a second conductive element included in a printed circuit board (PCB) is provided. The PCB comprises a plurality of conductive layers and a plurality of conductive elements, where each conductive layer comprises one or more conductive elements. The plurality of conductive layers comprises one or more outer conductive layers. The method comprises selecting a first conductive element (A) disposed on a first outer conductive layer and a second conductive element (B) disposed on a second outer conductive layer of the PCB, a clearance between which has a minimum spacing requirement. The method also comprises creating polygons of the first and second conductive elements, wherein a polygon of the first conductive element is A′ and a polygon of the second conductive element is B′. The method also comprises determining if there is at least one conductive layer disposed between A′ and B′. If no conductive layer is disposed between A′ and B′, then A″ and B″ are created on an evaluation layer. The method further comprises calculating a shortest unshielded distance (dxy) between A″ and B″. The method also comprises using a distance between the conductive layers (dz), and calculating a distance (d), wherein d=√{square root over (dxy2+dz2)}. If the calculated distance d is less than the minimum spacing requirement, a violation is indicated.

The invention discloses a circuit board production process management and control method and system based on a multilayer circuit. The method comprises the following steps: establishing an interlayer transmission line parameter model of a multilayer circuit board, and calculating electromagnetic field distribution based on a deformation telegraph equation and a parallel plate resonance effect; performing transmission characteristic simulation verification; optimizing production environment parameters, and selecting an area of which the electric field intensity is lower than 45% maximum value as a wiring optimal area; implementing a layered wiring strategy, and optimizing an interlayer wiring path according to the transmission matrix; production data are dynamically monitored, temperature, humidity and electromagnetic radiation data are collected in real time, and machining parameters are adjusted in combination with a transmission matrix correction value. According to the method, the transmission characteristics are accurately predicted, the production environment parameters are optimized, the influence of the external environment on the performance of the circuit board is effectively reduced, and the stability and reliability of the circuit board are improved. Through establishment of a parameter model and simulation verification, comprehensive management and control of the production process of the multilayer circuit board are realized.