224results about "Computer designed circuits" patented technology

The invention relates to the technical field of PCB processing, and discloses a multi-layer circuit board drilling method and device based on machine vision, and the method comprises the steps: obtaining a multi-layer circuit board image; preprocessing the multi-layer circuit board image to obtain a to-be-identified image; inputting the to-be-recognized image into a pre-trained defect detection model to obtain defect position data; carrying out point location identification and matching on the to-be-identified image to obtain an optimal hole location coordinate, and carrying out correction according to the optimal hole location coordinate to obtain hole location information data; according to the hole site information data and the defect position data, nodes are constructed respectively, distance calculation is carried out, and a hole site node graph is generated; according to the hole site node graph, performing path planning by applying an ant colony algorithm, and performing iterative search to obtain an optimal drilling path; and drilling the multilayer circuit board according to the optimal drilling path. The method has the following effect that the drilling efficiency of the multilayer circuit board can be improved.

The invention provides a method and system for preparing a high-temperature anti-aging test board for chip testing, and relates to the technical field of data energy storage and resource scheduling, and the method comprises the steps: designing a schematic circuit diagram and a PCB wiring scheme; a test plate is made of a high-temperature resistant material; bare board verification, electrical performance verification, program setting verification, high temperature verification and junction temperature measurement verification are carried out; using data is recorded, ultrasonic cleaning and drying are carried out, and a performance evaluation model is established through a hardware management system to judge whether maintenance or replacement is needed. According to the invention, the accuracy of chip testing in a high-temperature environment is improved, and the service life of the test board is prolonged.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

The invention provides an industrial circuit board intelligent repairing method and system based on a lossless damping chip, and the method comprises the steps: obtaining multi-dimensional acoustic response data in an industrial circuit board, carrying out the spatial analysis of a phase offset in the data, and generating a three-dimensional geometric boundary coordinate set of a microcrack region; activating a resonant wave stabilization processing mode of the lossless damping chip, and generating a mechanical resonant frequency and a dynamic constraint force field for inhibiting crack propagation; generating a target filling scheme according to the stress distribution state of the dynamic constraint force field; constructing a conductive filling path topological structure, and generating a continuous conductive interface; according to the resonance response characteristic between the continuous conductive interface and the mechanical resonance frequency, a micron-sized crack repairing scheme is generated, and intelligent repairing of the industrial circuit board is carried out. The method breaks through the problem of fuzzy positioning of the crack spatial form in the traditional detection technology; the accurate permeation of the filling material along the crack is ensured; verification and closed loop feedback of the repairing effect are achieved, and the stability and reliability of the repaired industrial circuit board are remarkably improved.

The invention relates to the technical field of circuit board processing, and discloses a circuit board back drilling stub control method, device and equipment and a medium, and the circuit board back drilling stub control method comprises the steps: carrying out the board thickness measurement of a circuit board, obtaining the original board thickness data, carrying out the difference analysis, and carrying out the piling and measurement processing according to the analysis result; obtaining a plate thickness data set corresponding to each pile; measuring and analyzing the target back drilling hole position to obtain grouped plate thickness data, calculating the influence degree of the plate thickness on the length of the back drilling stub, comparing the influence degree with a preset threshold value, and judging a back drilling depth adjusting scheme; and according to a judgment result, back drilling processing depth parameters of the whole or the partitions are calculated, and differentiated depth optimization control is achieved. According to the method, the stub range can be effectively reduced in multi-batch and high-layer PCB machining, the back drilling depth control precision is improved, and it is ensured that the stub length is stable and meets the high-specification signal integrity requirement.

The invention relates to the technical field of element bonding pad matching, in particular to a method for automatically matching a component and a bonding pad, which comprises the following steps of: directly and dynamically calculating a coverage area according to the size of the component, and detecting a bonding pad layer in real time without pre-storing a mapping relation; the electrical feasibility verification that the number of bonding pads is greater than or equal to the number of pins is increased to solve the risk of insufficient solder or solder skips; the coordinate correction is matched with the mean correction coordinate of the central point of the bonding pad, and the angle correction is realized by identifying a silk-screen polarity identifier through AI to realize a dual-stage correction technology; polarity identification consistency verification is newly added, so that the installation correctness of a high-reliability device is ensured, and polarity direction guarantee is realized; the workload of a client for pre-storing the template is reduced, and the matching precision is improved through dynamic detection and closed-loop correction.

The invention discloses a high-precision circuit board wet film processing method and system, and relates to the field of circuit board wet film processing, and the method comprises the complete manufacturing process of substrate pretreatment, wet film coating, LDI exposure, development, micropore etching and final film stripping. The key point is that a data barrier in a traditional process is broken through between LDI exposure and a downstream etching process. Specifically, key parameters of etching liquid are collected in real time in the etching stage, and an intelligent model capable of predicting the etching influence is constructed and continuously optimized in combination with an actual line width detection result of an etched plate. The model can be used for prospectively calculating an accurate dynamic etching compensation value according to the current state of the etching liquid, and feeding back the accurate dynamic etching compensation value to LDI equipment for adjusting the exposure line width. Therefore, the problem of compensation failure caused by etching liquid aging can be effectively solved, and the high consistency and stability of line width in cross-batch production are ensured.

The invention provides a neck copper area processing method and device in EDA design, equipment and a medium. The method comprises the steps that S110, an avoided copper sheet is obtained; s120, whether a neck copper area with the width smaller than a preset narrowest distance exists in the avoided copper sheet or not is recognized; and S130, if the neck copper area exists, cutting the neck copper area in the avoided copper sheet to obtain a cut copper sheet. According to the method, the ultra-fine area of the copper sheet after avoidance is identified through external expansion and intersection point solving of the convex polygon, the neck copper area is screened out by combining certain design detail requirements, and then the neck copper area is cut off through an operation function of the polygon with the hole, so that the quality and the efficiency of a circuit are ensured.

The invention discloses an intelligent dynamic control method and system for a V-CUT machining process, and the method comprises the steps: arranging a multispectral laser displacement sensor array at a V-CUT cutter shaft, arranging a high-frequency piezoelectric micro-touch probe at a residual thickness measurement station, and generating point cloud data in real time based on a preset sampling frequency; synchronously mapping the point cloud data into a digital twin model corresponding to the V-CUT equipment, and updating the V-CUT groove depth, the PCB residual thickness and the V-CUT knife edge wear degree corresponding to the twin model in real time; predicting a cutter shaft machining drifting trend according to the groove depth, the residual thickness and the cutter edge abrasion state; and when the drift trend predicted value exceeds the process threshold value, a feed-forward compensation instruction is issued to a cutter shaft servo system, and closed-loop correction in the V-CUT machining process is achieved. According to the invention, production and detection integration can be realized, individual manual detection by personnel after shutdown is not needed, and quality improvement and production efficiency maximization can be effectively ensured.

The embodiment of the invention relates to an electronic design automation data checking method and electronic equipment. The method comprises the steps that to-be-checked electronic design automation data and a checking configuration file are obtained respectively; the checking configuration file comprises checking rules for checking the electronic design automation data, and the checking rules are editable rules; the check rule is structured data, and the structured data comprises a rule check function; and checking the to-be-checked electronic design automation data based on the rule checking function to generate a checking result. The checking configuration file is an editable rule, so that the checking rule for checking the electronic design automation data to be checked can be determined based on the editing operation of the user, and the checking rule in the configuration file can be flexibly adjusted according to the requirement of the user; according to the embodiment of the invention, the situation that the inspection content is relatively single and does not have expansibility in related technologies can be avoided, so that the inspection efficiency of the electronic design automation data can be improved.

The invention provides a multilayer circuit board, a via hole structure optimization method and electronic equipment, and can be applied to the technical field of electronic equipment. The multilayer circuit board comprises a plurality of signal layers; the at least one first differential via hole structure is drilled in the multi-layer circuit board along a direction deviating from the normal direction of the multi-layer circuit board by a first drilling angle, so that at least two signal layers in the multiple signal layers in the multi-layer circuit board are electrically connected with each other; the at least one second differential via hole structure is drilled in the multi-layer circuit board in the direction deviating by a second drilling angle relative to the normal direction of the multi-layer circuit board, so that at least two signal layers in the multiple signal layers are electrically connected with each other; wherein the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via hole structure and the at least one second differential via hole structure intersect with each other.

The invention belongs to the technical field of electronic manufacturing and printed circuit boards, and particularly relates to a lamination method and system of a multilayer flexible circuit board, which comprises the steps of providing a flexible substrate layer, forming a graphical photosensitive layer, arranging a binder layer, stacking a multilayer structure, performing exposure development and lamination treatment and the like. The system comprises a material supply unit, a graphical photosensitive layer forming unit, a lamination stacking unit, a graphical processing unit and a lamination unit, and full-process automation is realized through a central control unit. According to the invention, the positioning and alignment precision can be improved, the material compatibility is optimized, the process integration level is enhanced, and the lamination quality is improved, so that the production efficiency and the product yield of the multi-layer flexible circuit board are remarkably improved.

The invention discloses a circuit board production process management and control method and system based on a multilayer circuit. The method comprises the following steps: establishing an interlayer transmission line parameter model of a multilayer circuit board, and calculating electromagnetic field distribution based on a deformation telegraph equation and a parallel plate resonance effect; performing transmission characteristic simulation verification; optimizing production environment parameters, and selecting an area of which the electric field intensity is lower than 45% maximum value as a wiring optimal area; implementing a layered wiring strategy, and optimizing an interlayer wiring path according to the transmission matrix; production data are dynamically monitored, temperature, humidity and electromagnetic radiation data are collected in real time, and machining parameters are adjusted in combination with a transmission matrix correction value. According to the method, the transmission characteristics are accurately predicted, the production environment parameters are optimized, the influence of the external environment on the performance of the circuit board is effectively reduced, and the stability and reliability of the circuit board are improved. Through establishment of a parameter model and simulation verification, comprehensive management and control of the production process of the multilayer circuit board are realized.

Disclosed is a computer-implemented method for degassing for the manufacture of a high speed design. The method includes analyzing information related to a printed circuit board (PCB) that includes a set of layers and a plurality of voids. The method identifies a void from the plurality of voids, where the void has a position among the PCB set of layers. The method determines a radius associated with the identified void, where the radius is based on a center of the identified void. The method performs a trace selection and executes a shift algorithm based on the trace selection, where the shift algorithm includes a modification of the information related to the void. As a result, the method can generate a grid for degassing based on execution of the shift algorithm. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a high-isolation low-loss filtering structure and method for a PCB strip line. According to the high-isolation low-loss filtering structure provided by the invention, the main transmission strip line, the filtering auxiliary strip line with the spur line structure and the grounding layer with the hollowed-out area are integrated in the PCB, so that external discrete filter elements and welding procedures and shielding separation cavities required by the external discrete filter elements are effectively omitted, and therefore, the size of a module is remarkably reduced; weight and complexity. Meanwhile, due to the integrated design, impedance discontinuity and signal reflection caused by the fact that signals are converted between the inner layer and the surface layer of the PCB through the via holes are avoided, and signal integrity is guaranteed. And finally, on the premise of not introducing additional elements, high-performance filtering is realized, and an effective solution is provided for miniaturization and high performance of the radio frequency front-end module.

The invention discloses an automatic fixing and sealing system and method for a circuit board, and relates to the technical field of printed circuit processes. The method comprises the steps that a device height point set is collected, and a center line coordinate set, a width set and a coating forbidding coordinate set are obtained through extraction; calculating an entrance truncation level according to the center line coordinate set and the width set, calculating a drift candidate coordinate set according to the device height point set and the width set, and generating a limited deposition partition table; generating a limited deposition instruction based on the limited deposition partition table, the entry truncation level and the drift candidate coordinate set; driving a nozzle to form an inlet barrier layer along an inlet barrier track according to a limited deposition instruction, forming a barrier belt on the outer side of the coating forbidding coordinate set, performing injection deposition according to an injection discharge sequence and a guide airflow sequence, and inhibiting a drift candidate coordinate set according to a recovery airflow sequence; outputting solid sealing record data; the method can deal with material transport mechanism switching caused by a narrow channel geometric structure, and avoids limitation of traditional two-dimensional trajectory optimization.

The embodiment of the invention discloses a PCB impedance compensation design method and device, equipment and a storage medium. The method comprises the steps that the impedance line width and the line spacing of each line layer in a PCB are acquired; determining the maximum film compensation amount and the minimum film spacing of the compensation design under the circuit layer thickness corresponding to each circuit layer in the PCB; performing first compensation on the film compensation value of each circuit layer in the PCB according to the maximum film compensation amount; and performing second compensation on the film compensation value of the line layer of which the actual distance of the impedance line does not meet the compensation condition in each line layer of the PCB. According to the invention, the effect of improving the impedance design yield is achieved.

The invention relates to a method for producing a measuring means having a layer composite, wherein: the conductor track layer and the isolation layer are joined together to form an initially deformable layer composite; the joining is in particular an integral joining; the layer composite is applied over a surface of a part or of the further part of the measuring means, in particular by integral bonding; and the conductor track of the conductor track layer extends in alignment with a profile of the surface at least in portions; in particular the layer composite is applied in such a way that the isolation layer isolates the conductor track layer from the surface.

The invention discloses a printed circuit board, a server, a wiring compensation method and device, equipment and a medium, and relates to the technical field of circuit boards, and the printed circuit board is provided with at least two signal transmission lines; each signal transmission line comprises a plurality of transmission line sections which are connected in sequence, different transmission line sections of the same signal transmission line have different unit length transmission time delays, the transmission line sections of different signal transmission lines are oppositely arranged, and the unit length transmission time delays of the opposite transmission line sections are the same; any two opposite transmission line segments are a transmission line segment to be adjusted and a target transmission line segment, the transmission line segment to be adjusted further comprises a plurality of compensation line segments, and the compensation line segments are inserted between parallel segments of the transmission line segment to be adjusted so that the lengths of any two opposite transmission line segments can be the same. According to the invention, the consistency of signal transmission delays of the two signal transmission lines is ensured, and signals transmitted by the two signal transmission lines arrive at the same time, so that the signal integrity design quality can be greatly improved.

This application discloses a line width determination method, electronic device, and storage medium, relating to the field of server technology. The method comprises: obtaining a preset line width corresponding to a pin, where the preset line width is the width of a pin trace corresponding to the pin, through which the pin is connected to a circuit board; determining the pin width of the pin, where the pin width is the width of the area occupied by the pin on the circuit board after the pin is connected to the circuit board; and determining a target line width for the pin trace based on the preset line width and the pin width. In the above method, the target line width of the pin trace can be flexibly adjusted based on the preset line width and the pin width, thereby improving the soldering reliability of the pin.

The invention provides a vehicle-mounted controller partition PCB layout and system for suppressing electromagnetic interference, and relates to the field of PCB layout, and the method comprises the steps: dividing a controller into a high-speed digital domain, an analog sampling domain, a radio frequency communication domain, a power conversion domain and the like in a design stage, and analyzing the backflow path and noise characteristics of the controller; generating a verifiable pseudo-random ground copper topology according to the unique identification information so as to destroy a periodic resonance condition and keep low-frequency backflow continuous; polarization channel mapping is established through a directional via array and an in-layer conductor so as to realize spatial polarization isolation; after manufacturing, performing impedance spectrum, reference voltage and polarization distribution detection to confirm the electromagnetic performance; the design seeds and detection data of the qualified board are written into a traceability database to support reproducible production; during assembly, the segmented cover bodies are pressed in the polarization direction to form multi-stage shielding.

Embodiments of the present application disclose a PCB pin mark processing method, device and equipment and a storage medium. The method comprises the following steps: in response to a received first detection processing instruction, determining a target component in a PCB layout, position information of a first pin mark of the target component, and position information of design elements in the PCB layout except the first pin mark; according to the position information of the first pin mark, the position information of the design elements and a preset overlap condition, confirming an overlap state of the first pin mark and the design elements; and if the first pin mark and the design elements are confirmed to be in the overlap state, adjusting the first pin mark with a pin corresponding to the first pin mark as the center. The scheme can quickly modify and process the first pin mark meeting the overlap condition, thereby improving the processing efficiency.

Specifically disclosed in the present invention is a processing method for a printed circuit board with an arc-shaped corner. The method comprises the following steps: S1, on the basis of clearance requirements of a printed circuit board, determining the radian of an arc-shaped corner to be processed, and then calculating the stress situation of the outermost edge position point of the radian of the arc-shaped corner; S2, on the basis of the stress situation of the outermost edge position point of the radian of the arc-shaped corner, determining a safe position point for the placement of a solder pad on the top surface of the printed circuit board; S3, on the basis of the arc-shaped corner, determining a wiring-forbidden area on the bottom surface of the printed circuit board; and S4, on the basis of the radian of the arc-shaped corner, selecting an arc-shaped milling cutter having a corresponding radian to process a pre-designed printed circuit board, so as to obtain a printed circuit board having the arc-shaped corner. By means of calculating the stress borne by a printed circuit board, the present invention realizes the effective clearance for a device while ensuring the reliability of a product, improves the integration level of the device, reduces the space a single functional module occupies on a mainboard, and thus reduces the area of the mainboard, and more space can be provided for mounting other components.

The application belongs to the technical field of electronic manufacturing and printed circuit board, and particularly relates to a laminating method and system for a multilayer flexible circuit board, which comprises the following steps: providing a flexible substrate layer, forming a patterned photosensitive layer, arranging an adhesive layer, stacking a multilayer structure, performing exposure and development, and laminating, etc. The system comprises a material supply unit, a patterned photosensitive layer forming unit, a laminated stacking unit, a patterned processing unit and a laminating unit, and realizes full-process automation through a central control unit. The application can improve positioning and alignment accuracy, optimize material compatibility, enhance process integration, improve laminating quality, and thus significantly improve the production efficiency and product yield of the multilayer flexible circuit board.

A printed circuit board (PCB) wiring automatic design method in a PCB wiring automatic design system, the system including at least one processor and at least one memory including an instruction, and the PCB wiring automatic design method performed in cooperation with the instruction, the memory, and the processor, includes: receiving PCB data including a net list and information on a plurality of terminals; updating a cost of a wiring exploration region so that a cost of at least some of the wiring exploration region is increased based on a preset constraint condition; exploring a shortest path for wiring the plurality of terminals according to the net list in a cost-updated wiring exploration region; and performing wiring of the plurality of terminals based on wiring probability according to the shortest path.

The application discloses a signal layer exchange structure optimization method and device suitable for a DDR5 printed circuit board, equipment, medium and product, relates to the signal layer exchange structure optimization field, and the method comprises the following steps: obtaining the signal layer exchange structure of the DDR5 printed circuit board and target impedance values corresponding to surface layer traces and inner layer traces in the signal layer exchange structure; establishing an equivalent transmission line model according to basic structure parameters of the signal layer exchange structure in the vertical direction of the printed circuit board; performing time-domain reflection impedance simulation on the equivalent transmission line model in a transient solution mode to obtain actual impedance values; and adjusting the layer exchange conductor width in the signal layer exchange structure and the parallel distance between the layer exchange conductor and the vertical GND reference layer according to the difference between the actual impedance values and the target impedance values to obtain an optimized signal layer exchange structure. The application can improve the quality, stability and transmission characteristics of signal transmission.

According to the large-size substrate long-distance interconnection wiring structure design method provided by the invention, the signal integrity problem in large-size substrate long-distance interconnection is optimized through a multi-layer wiring structure, and the adaptability to higher communication bandwidth is improved. Taking a double-layer wiring structure as an example, the left and right sides of the wiring structure are respectively provided with a ground wire, the middle of the wiring structure is provided with a pair of differential signal wires, and each signal wire adopts two metal layers and can be equivalent to parallel connection of two metal wires, so that direct-current impedance is halved, and the problems of large direct-current impedance and high insertion loss in signal integrity are solved; besides, the multi-layer wiring structure surrounds and isolates a pair of differential signal lines by arranging a ground wire on each of the left side and the right side, so that the crosstalk influence of bypass signal lines on the differential signal lines under high frequency is reduced, and the problem of far-end crosstalk in signal integrity is solved; in addition, the multi-layer wiring structure can be flexibly adjusted, so that the requirements of different design cases can be met.

The present application relates to the technical field of printed circuit board design, and discloses a via arrangement method, device, equipment and storage medium for a printed circuit board, including: for two signal vias corresponding to a group of high-speed differential signals, a ground network return via is arranged at the middle position between the two signal vias; the two signal vias share one ground network return via; for four signal vias corresponding to two groups of high-speed differential signals, a ground network return via is arranged at the middle position among the four signal vias; wherein, the four signal vias share one ground network return via. In the design of the via arrangement structure for high-speed differential signals to change layers, the present application only arranges one corresponding ground network return via for one or two groups of high-speed differential signals, that is, enables two or four signal vias to share one ground network return via, thereby simplifying the single-board design to improve the space utilization rate of the single board, and reducing the space occupied by high-speed differential signals while meeting the electrical performance requirements.

The invention relates to the technical field of semiconductor packaging manufacturing and intelligent detection, in particular to a digital twinning fused MINI LED solder paste printing parameter optimization method, which comprises the following steps: a reference construction step: obtaining a Gerber file and steel mesh aperture data, and reconstructing a defect-free pure ideal state; a simulation generation step: establishing a parameter and deformation mapping model, and generating a plurality of theoretical disturbed simulation states; a difference calculation step: collecting actual solder paste detection data, and determining an actual deviation tensor and a theoretical deviation tensor; a parameter locking step: calculating a spatial similarity numerical value of the two, if the spatial similarity numerical value exceeds a threshold value, locking the corresponding printing parameter as a physical cause, and generating a reverse compensation instruction to adjust the printing machine parameter; according to the method, the physical reference frame is constructed, so that the manufacturing tolerance noise of the bonding pad is effectively filtered out, and accurate tracing of physical causes of printing defects in a micro-pitch process is realized.