81results about "Computer designed circuits" patented technology

The invention discloses a high-isolation low-loss filtering structure and method for a PCB strip line. According to the high-isolation low-loss filtering structure provided by the invention, the main transmission strip line, the filtering auxiliary strip line with the spur line structure and the grounding layer with the hollowed-out area are integrated in the PCB, so that external discrete filter elements and welding procedures and shielding separation cavities required by the external discrete filter elements are effectively omitted, and therefore, the size of a module is remarkably reduced; weight and complexity. Meanwhile, due to the integrated design, impedance discontinuity and signal reflection caused by the fact that signals are converted between the inner layer and the surface layer of the PCB through the via holes are avoided, and signal integrity is guaranteed. And finally, on the premise of not introducing additional elements, high-performance filtering is realized, and an effective solution is provided for miniaturization and high performance of the radio frequency front-end module.

The invention discloses an automatic fixing and sealing system and method for a circuit board, and relates to the technical field of printed circuit processes. The method comprises the steps that a device height point set is collected, and a center line coordinate set, a width set and a coating forbidding coordinate set are obtained through extraction; calculating an entrance truncation level according to the center line coordinate set and the width set, calculating a drift candidate coordinate set according to the device height point set and the width set, and generating a limited deposition partition table; generating a limited deposition instruction based on the limited deposition partition table, the entry truncation level and the drift candidate coordinate set; driving a nozzle to form an inlet barrier layer along an inlet barrier track according to a limited deposition instruction, forming a barrier belt on the outer side of the coating forbidding coordinate set, performing injection deposition according to an injection discharge sequence and a guide airflow sequence, and inhibiting a drift candidate coordinate set according to a recovery airflow sequence; outputting solid sealing record data; the method can deal with material transport mechanism switching caused by a narrow channel geometric structure, and avoids limitation of traditional two-dimensional trajectory optimization.

The invention provides a vehicle-mounted controller partition PCB layout and system for suppressing electromagnetic interference, and relates to the field of PCB layout, and the method comprises the steps: dividing a controller into a high-speed digital domain, an analog sampling domain, a radio frequency communication domain, a power conversion domain and the like in a design stage, and analyzing the backflow path and noise characteristics of the controller; generating a verifiable pseudo-random ground copper topology according to the unique identification information so as to destroy a periodic resonance condition and keep low-frequency backflow continuous; polarization channel mapping is established through a directional via array and an in-layer conductor so as to realize spatial polarization isolation; after manufacturing, performing impedance spectrum, reference voltage and polarization distribution detection to confirm the electromagnetic performance; the design seeds and detection data of the qualified board are written into a traceability database to support reproducible production; during assembly, the segmented cover bodies are pressed in the polarization direction to form multi-stage shielding.

Embodiments of the present application disclose a PCB pin mark processing method, device and equipment and a storage medium. The method comprises the following steps: in response to a received first detection processing instruction, determining a target component in a PCB layout, position information of a first pin mark of the target component, and position information of design elements in the PCB layout except the first pin mark; according to the position information of the first pin mark, the position information of the design elements and a preset overlap condition, confirming an overlap state of the first pin mark and the design elements; and if the first pin mark and the design elements are confirmed to be in the overlap state, adjusting the first pin mark with a pin corresponding to the first pin mark as the center. The scheme can quickly modify and process the first pin mark meeting the overlap condition, thereby improving the processing efficiency.

A printed circuit board (PCB) wiring automatic design method in a PCB wiring automatic design system, the system including at least one processor and at least one memory including an instruction, and the PCB wiring automatic design method performed in cooperation with the instruction, the memory, and the processor, includes: receiving PCB data including a net list and information on a plurality of terminals; updating a cost of a wiring exploration region so that a cost of at least some of the wiring exploration region is increased based on a preset constraint condition; exploring a shortest path for wiring the plurality of terminals according to the net list in a cost-updated wiring exploration region; and performing wiring of the plurality of terminals based on wiring probability according to the shortest path.

The application discloses a signal layer exchange structure optimization method and device suitable for a DDR5 printed circuit board, equipment, medium and product, relates to the signal layer exchange structure optimization field, and the method comprises the following steps: obtaining the signal layer exchange structure of the DDR5 printed circuit board and target impedance values corresponding to surface layer traces and inner layer traces in the signal layer exchange structure; establishing an equivalent transmission line model according to basic structure parameters of the signal layer exchange structure in the vertical direction of the printed circuit board; performing time-domain reflection impedance simulation on the equivalent transmission line model in a transient solution mode to obtain actual impedance values; and adjusting the layer exchange conductor width in the signal layer exchange structure and the parallel distance between the layer exchange conductor and the vertical GND reference layer according to the difference between the actual impedance values and the target impedance values to obtain an optimized signal layer exchange structure. The application can improve the quality, stability and transmission characteristics of signal transmission.

The invention relates to the technical field of semiconductor packaging manufacturing and intelligent detection, in particular to a digital twinning fused MINI LED solder paste printing parameter optimization method, which comprises the following steps: a reference construction step: obtaining a Gerber file and steel mesh aperture data, and reconstructing a defect-free pure ideal state; a simulation generation step: establishing a parameter and deformation mapping model, and generating a plurality of theoretical disturbed simulation states; a difference calculation step: collecting actual solder paste detection data, and determining an actual deviation tensor and a theoretical deviation tensor; a parameter locking step: calculating a spatial similarity numerical value of the two, if the spatial similarity numerical value exceeds a threshold value, locking the corresponding printing parameter as a physical cause, and generating a reverse compensation instruction to adjust the printing machine parameter; according to the method, the physical reference frame is constructed, so that the manufacturing tolerance noise of the bonding pad is effectively filtered out, and accurate tracing of physical causes of printing defects in a micro-pitch process is realized.

The invention discloses a circuit board V-CUT numerical control machining method adaptive to multi-specification board materials. The circuit board V-CUT numerical control machining method adaptive to the multi-specification board materials comprises the following steps that S1, a circuit board to be machined is fed to a V-CUT numerical control machining system; s2, task selection; s3, gating and initialization are carried out; s4, performing visual identification and positioning; s5, self-adaptive clamping is carried out; s6, tool detection and compensation; s7, automatic tool setting; s8, generating a self-adaptive path; s9, intelligent V-CUT machining is carried out; s10, machining is completed, and resetting is carried out; and S11, an operator opens a safety door and takes out the machined plate. According to the circuit board V-CUT numerical control machining method adaptive to the multi-specification board materials, a high-definition image is shot through a machine vision unit, a reference Mark point is extracted, the actual position deviation (delta X, delta Y and delta theta) of the board materials is calculated, through deviation calculation based on a coordinate transformation algorithm, the placement error during board material feeding is eliminated, and the board material quality is improved. And accurate matching of the machining path and the actual position of the plate is ensured.

The invention discloses a packaging method and system of a power electronic component for automobile circuit board processing, and relates to the technical field of power electronic packaging, and the method comprises the steps: carrying out the preprocessing of an automobile circuit board, and generating the to-be-processed information of the automobile circuit board; the power electronic component is fixed to a preset position of the automobile circuit board to be electrically connected, and welding assembly parameters are obtained; encapsulating the power electronic component to generate an encapsulation component parameter; and performing a multi-dimensional packaging performance test based on the packaging component parameters, performing process backtracking according to a multi-dimensional test result, positioning target packaging process parameters for dynamic adjustment, and obtaining a packaging quality report of the power electronic component. The technical problems that a traditional packaging method does not adapt to the characteristics of an automobile circuit board carrier and the requirements of related components, control over all links is not accurate, and data acquisition is not comprehensive are solved, and the technical effects that packaging quality data are comprehensively acquired and accurately evaluated, and packaging reliability and quality control efficiency are improved are achieved.

Disclosed is a computer-implemented method for degassing for the manufacture of a high speed design. The method includes analyzing information related to a printed circuit board (PCB) that includes a set of layers and a plurality of voids. The method identifies a void from the plurality of voids, where the void has a position among the PCB set of layers. The method determines a radius associated with the identified void, where the radius is based on a center of the identified void. The method performs a trace selection and executes a shift algorithm based on the trace selection, where the shift algorithm includes a modification of the information related to the void. As a result, the method can generate a grid for degassing based on execution of the shift algorithm. Various other methods, systems, and computer-readable media are also disclosed.

The invention discloses a PCB (Printed Circuit Board) design method based on a key wiring bonding pad non-damage test and a PCB jointed board, and relates to the technical field of PCB bonding pad detection. Comprising a plurality of unit boards, a first connecting piece, a second connecting structure and a frame, and each unit board comprises a first key wiring unit and a first key wiring bonding pad; the frame comprises a transverse plate and an edge plate, and the edge plate is connected with the transverse plate through a second connecting structure; the edge plate is provided with a test unit, and the test unit comprises a second key wiring unit corresponding to the first key wiring unit and a second key wiring bonding pad corresponding to the first key wiring bonding pad. The key bonding pad on the unit board is not contacted, so that'damage-free test 'is realized. Moreover, the edge plate is connected with the transverse plate through the second connecting structure, so that the edge plate can be separated from the frame body, the separated test units can be archived for future reference, and the whole-process monitoring and tracing of the production quality are realized.

The application relates to the technical field of circuit element layout, in particular to an element layout system of a DC-DC power module, which obtains a candidate position range according to a first preset position range and a second preset position, obtains a reference distance according to an initial value set, a target value, a preset wiring width and a preset dielectric constant, comprehensively considers different distance and angle combinations to generate a series of possible candidate positions, facilitates comprehensive exploration of the layout possibility of a target element on a target printed circuit board, respectively obtains an output voltage sequence and a response delay time corresponding to each candidate position to represent the stability, accuracy, reliability and timeliness of the circuit under different candidate positions, and then obtains a target priority corresponding to each candidate position, determines the candidate position corresponding to the maximum target priority as the target position of the target element, improves the layout rationality of the target element, and further improves the performance and reliability of the entire circuit.

The present application relates to the technical field of printed circuit boards, and provides a differential signal transmission circuit, a circuit board, an electronic device, and a circuit manufacturing method. For the differential signal transmission circuit, the following is formed on a surface layer of a circuit board: a peripherally closed pattern, a first pattern, a second pattern, and a third pattern; the first pattern, the second pattern, and the third pattern are all surrounded by the peripherally closed pattern; the first pattern, the second pattern, and the third pattern are isolated by a dielectric; the first pattern and the second pattern are axisymmetric; the first pattern and the second pattern are respectively connected to an inner signal layer by means of an inner wall plating layer of the circuit board; and the third pattern is used to form a return current path.

The invention is suitable for the technical field of back drilling, and provides a method for obtaining back drilling control data, a controller and back drilling machining equipment. The method for obtaining the back drilling control data comprises the steps of obtaining hole center coordinates, corresponding to the upper surface and the lower surface of a circuit board, of a drilled through hole, and determining the hole center coordinates, corresponding to the upper surface and the lower surface, of the drilled through hole in a back drilling stop layer based on the hole center coordinates corresponding to the upper surface and the lower surface, according to the depth of the back drilling stop layer and the hole center coordinate of the first-drilled through hole in the back drilling stop layer, back drilling control data is determined, the back drilling control data is used for enabling the center of a drill bit to be aligned with the hole center coordinate of the first-drilled through hole in the back drilling stop layer, the back drilling control precision can be improved, Stub asymmetry is reduced, and signal transmission integrity can be improved.

The application discloses a PCB defect correction method and a circuit board manufacturing method. The correction method comprises the following steps: inputting the design document of the circuit board to be detected into an AOI device, wherein the design document comprises the size design information of each object on the circuit board; scanning the circuit board by using the AOI device to obtain a scanning image, and acquiring the pixel unit size currently set by the AOI device; in response to a detection request for a target object on the circuit board, determining the number of pixels occupied by the target object in the scanning image in a requested measurement direction; calculating the size of the target object in the requested measurement direction according to the current pixel unit size of the AOI device and the number of pixels occupied by the target object; comparing the size of the target object in the requested measurement direction with the size of the target object in the design document; if the size difference exceeds a preset difference threshold, it is determined that the target object has a defect, and the process type of the target object is determined and the process parameter of the target object is corrected according to the design document.

The present disclosure provides a circuit structure (100), an electronic device, and a mutual-capacitance structure design method. The circuit structure (100) comprises a carrier plate (1) and a plurality of signal pads (2) arranged on the carrier plate (1), and the circuit structure (100) further comprises mutual-capacitance structures (3) arranged on the carrier plate (1), wherein each mutual-capacitance structure (3) has a first end (31), a second end (32), and a mutual-capacitance coupling portion (33) located between the first end (31) and the second end (32), and the first end (31) and the second end (32) of each mutual-capacitance structure (3) are respectively connected to two of the plurality of signal pads (2).

The invention is suitable for the technical field of converters, and provides an energy storage converter and a capacitor current sharing design method thereof. The energy storage converter comprises a PCB. The positive bus and the negative bus are arranged on the PCB, the reference midpoint is located between the positive bus and the negative bus, the first capacitor network is arranged between the positive bus and the reference midpoint and comprises a plurality of positive bus capacitors, and the second capacitor network is arranged between the reference midpoint and the negative bus and comprises a plurality of negative bus capacitors. The plurality of positive bus capacitors are connected in parallel, and the plurality of negative bus capacitors are connected in parallel; and the contact areas of the pins of the plurality of positive bus capacitors and the plurality of negative bus capacitors and the copper sheet on the PCB are different, so that a plurality of impedance gradients are formed. By the adoption of the mode, the current sharing precision can be improved, current sharing control is converted from circuit-level intervention to structure-level self-balancing, active elements such as current sharing resistors / inductors are omitted, and the current sharing circuit can adapt to high-frequency application scenes.

This invention discloses an automatic sealing system and method for circuit boards, relating to the field of printed circuit technology. The method includes: acquiring a set of device height points, extracting a centerline coordinate set, a width set, and a no-coating coordinate set; calculating the entry cutoff level based on the centerline coordinate set and the width set, calculating the drift candidate coordinate set based on the device height point set and the width set, and generating a restricted deposition partition table; generating a restricted deposition command based on the restricted deposition partition table, the entry cutoff level, and the drift candidate coordinate set; driving the nozzle along the entry barrier trajectory to form an entry barrier layer according to the restricted deposition command, forming a barrier band outside the no-coating coordinate set, and injecting deposition according to the injection and discharge sequence and the guiding airflow sequence, and suppressing the drift candidate coordinate set according to the recovery airflow sequence; and outputting sealing record data. This invention can cope with the switching of material transport mechanisms caused by narrow channel geometry, avoiding the limitations of traditional two-dimensional trajectory optimization.

The invention discloses an impedance coupon characterization method, an impedance coupon and a PCB in the field of PCB manufacturing impedance coupon design, and the method comprises the steps: obtaining the copper thickness of a continuous superposition layer to determine a power supply layer, and analyzing a copper-free region in the power supply layer to determine the arrangement type of a segmentation gap; determining a signal layer according to the power supply layer, obtaining an impedance line and a necking layer structure corresponding to the signal layer, and extracting a structure factor related to impedance; the impedance lines, the necking layers and the segmentation gaps are arranged on the impedance coupon according to corresponding factors, and combined design is carried out, so that the impedance coupon capable of representing the impedance characteristic of the signal layer under the segmentation gap superposition condition is constructed; according to the invention, through impedance coupon, the representativeness and reliability of the impedance test on the actual impedance state in the PCB can be improved.

The invention discloses an electronic component positioning method and device, equipment and a storage medium. Comprising the following steps: acquiring a design related file of a circuit board, and constructing an electronic component virtual matrix according to the design related file; a target component number input by a user is received, and retrieval is carried out in the electronic component virtual matrix; and when the retrieval is successful, scanning a minimum matrix containing LED lamps in the virtual matrix of the electronic component based on the target component, and lightening the LED lamps on the minimum matrix in the circuit board so as to position the target component. Scattered component positions on a circuit board are converted into a digital matrix, so that ordered management of the component positions is realized. By numbering the positions of the components in the matching matrix, manual consulting of technical documents or troubleshooting of the components one by one is not needed, and the retrieval efficiency is improved. The approximate range of the target component is locked through minimum matrix scanning, visual prompt is formed by lighting of the LED lamps, the area where the target component is located is rapidly determined, and the positioning accuracy is improved.

The invention discloses a printed circuit board laminated structure of a driving mode selection controller and a design method of the printed circuit board laminated structure. The laminated structure sequentially comprises a top layer, a grounding layer, a power signal layer and a bottom layer from top to bottom, wherein the top layer is used for laying circuit devices; the grounding layer is used for providing a reference ground signal; the power supply signal layer is used for laying a key power supply plane and key signal wires, and the bottom layer is used for laying a common power supply plane and common signal wires; a grounding pin of the circuit device in the top layer is connected to the grounding layer through a via hole, and a signal pin and a power supply pin of the circuit device are connected to the power supply signal layer and the bottom layer through via holes. According to the invention, through lamination planning of the power supply layer, the signal layer and the ground layer, mixed wiring of the signal lines on the power supply layer is realized, and the ground layer provides a reference plane for the device layer and the power supply signal layer, so that the number of laminated layers of the printed circuit board is effectively reduced, and the development cost can be saved.

The invention discloses a method for solving warping of a ceramic-based printed board and related equipment, and aims to overcome the defect of warping of a ceramic substrate caused by lack of an automatic copper foil balancing means in the prior art. The method comprises the following steps: firstly, acquiring copper area data of top and bottom layer patterns of the ceramic substrate and calculating a residual copper rate difference value; judging whether the difference value exceeds a preset threshold value or not; and if the residual copper rate exceeds the threshold value, automatically generating an auxiliary copper-clad pattern in a non-effective circuit area, then recalculating the difference value, and circulating the process until the residual copper rate difference value meets the threshold value requirement, thereby automatically balancing the stress of the inner layer and the outer layer, and fundamentally inhibiting the warping of the plate.

The invention relates to the technical field of printed circuit board manufacturing, in particular to a method for etching a PCB based on laser and machinery. Comprising the steps of S1, material preparation; s2, graphic design; s3, shunt design is carried out; s4, setting laser parameters; s5, performing laser etching; s6, mechanical carving; according to the laser and mechanical two-in-one PCB etching method, large-area copper removal or copper removal with a large line width and a large line spacing is realized by using mechanical polishing and cutting through process division, and a fine line with a small line width and a small line spacing is completed by laser engraving, so that the efficiency, the precision and the environmental protection are considered, and the two-in-one realization efficiency is higher; chemical liquid medicine is not needed in the whole process, discharge of heavy metal and organic waste liquid is avoided, the method is green and environment-friendly, mask and wet process processes are omitted, and the cost is saved; and the short-pulse ultraviolet laser is adopted to directly etch the circuit pattern on the copper-clad substrate, so that the method has the advantage of high precision, and is suitable for manufacturing high-end PCBs such as high-density interconnection boards, flexible boards, high-frequency and high-speed boards and the like.

The invention relates to an optimization method for manufacturing a rotary deployable curved plate, which belongs to the technical field of printed circuit board manufacturing, and comprises the following steps of: converting 3D (three-dimensional) coordinates of a client into 2D (two-dimensional) coordinates according to a 3D-2D (three-dimensional) transformation formula of coordinates corresponding to the appearance of a curved PCB (printed circuit board) to obtain a D code manuscript containing the positions, shapes or sizes of holes, bonding pads and leads during graph display and wiring, and realizing curvature adaptation of graph transfer; then, a curved surface supporting mold is used for being attached to the back face of the curved surface PCB, it is ensured that a base material is free of local collapse during drilling, meanwhile, a temporary back plate is added to enhance local rigidity, and curvature constraint before drilling is achieved; coordinates in the hole dividing graph are converted into cylindrical coordinates through a corresponding coordinate 2D-3D conversion formula, a drilling coordinate file and a 3D tool path file are generated, a drill bit or an end mill always points to the projection of a hole site on a generatrix, it is ensured that the hole site precision is matched with the curvature of a milling plate after rewinding, and low-rotating-speed high-feeding segmented pecking drilling is adopted, so that the machining precision is improved. Heat accumulation and lateral force are reduced.

The invention discloses a cutting path planning method and a cutting path planning system for a PCB (Printed Circuit Board), and relates to the technical field of PCB manufacturing. Image information of the PCB is acquired through a visual identification system and is transmitted to an AI image identification module, an AI algorithm is used for carrying out image identification and intelligent marking on connecting ribs, and a graph is fed to a model for training after confirmation; the method comprises the steps of image recognition and automatic path generation, automatic generation of an optimized cutting path, automatic cutting path issuing and execution module, automatic transmission of recognized path data to a board separator execution unit by a system, no manual debugging is needed, rapid recognition and path planning can be carried out on PCBs of various specifications and various shapes, and the production efficiency is improved. Intelligent switching, real-time correction and a self-learning mechanism of batch processing of different products are supported, the system has error feedback and model self-learning capabilities, and the recognition precision and efficiency are improved along with the use time. The whole system realizes closed-loop control, so that the manual intervention time is greatly reduced, and the system intelligence is improved.

The present application relates to the technical field of HDI printed circuit board processing, in particular to a processing method for solving the problems of copper surface residual glue and small size of binding PAD in cavity product position, after laser cavity processing, the characteristic vector is input into the trained gradient boosting regression tree (GBRT) model, and the adaptive plasma parameter is output, and the cavity copper surface is treated by adopting the adaptive plasma parameter; the present application realizes the dynamic matching of residual glue characteristics and treatment parameters by adopting the GBRT model to adaptively output the plasma parameter and combining with the sand blasting path planned by the A* algorithm; wherein the prediction error of the GBRT model to the plasma parameter is less than or equal to 5%, the priority coverage of the region to be optimized is ensured, the path overlap rate is less than or equal to 5%, the final residual glue removal rate is improved to more than 98%, and the problem of incomplete treatment of traditional fixed parameters is solved.

The invention relates to a circuit board with special-shaped quantity targets and a windowing method, and belongs to the technical field of circuit boards, the circuit board comprises an inner-layer special-shaped quantity target graph, main positioning holes and an auxiliary positioning graph group which are arranged on the circuit board, the main positioning holes are arranged in four corner areas of the circuit board, and the auxiliary positioning graph group is arranged in the inner-layer special-shaped quantity target graph. The auxiliary positioning graph group comprises a center auxiliary positioning graph, an edge auxiliary positioning graph and a target adjacent auxiliary positioning graph, and the center auxiliary positioning graph is arranged at the geometric center of the circuit board; the edge auxiliary positioning patterns are arranged in the middle areas of the plate edges between the adjacent main positioning holes; the target is adjacent to the auxiliary positioning pattern and is arranged on the peripheral side of the inner-layer special-shaped quantity target pattern. The special-shaped features of different positions of the center, the board edge and the periphery of the target of the circuit board are captured in a targeted manner through the auxiliary positioning pattern group, the complex deformation conditions of nonlinear stretching, local warping and X / Y direction unequal ratios after the substrate is pressed can be comprehensively reflected, the detection coverage of the special-shaped quantity is more comprehensive, and the special-shaped quantity is more close to the actual deformation state.

The invention discloses a joint simulation-based SiC parallel power board optimal configuration method and system. The method comprises the following steps: step S01, obtaining initial PCB layout configuration formed by sequentially arranging SiC parallel power boards according to design requirements; s02, generating a PCB file for the current PCB layout configuration, performing stray parameter simulation on the generated PCB file, comparing stray parameters obtained by simulation with a stray parameter reference value, and if the stray parameters do not meet the preset requirement, adjusting the PCB layout configuration until the stray parameters meet the preset requirement; and S03, establishing a SiC device circuit model according to the PCB layout configuration obtained by simulation and the stray parameters, performing simulation, judging whether the grid waveform meets a preset requirement, and if not, adjusting the PCB layout to obtain the final SiC parallel power board layout configuration. The method has the advantages of being simple in implementation method, low in cost, high in execution efficiency and mobility and the like.

The invention relates to the technical field of machine learning, and provides a high-precision PCB pressing control method based on machine learning, and the method comprises the steps: collecting the technological index parameters of target PCB pressing equipment in a historical period; analyzing the characterization value of the process index; based on a comparison result of the process index characterization value and a preset process index characterization threshold value, whether the operation process of the target PCB pressing equipment meets the standard or not is determined; in response to the condition that the operation process of the target PCB pressing equipment meets the standard, collecting quality index parameters of the target PCB pressing equipment in a historical period; analyzing the characterization value of the quality index; determining whether the target PCB pressing equipment meets a risk assessment standard or not based on a difference result between the quality index characterization value and a preset quality index characterization threshold value; and determining a processing strategy based on the quality index characterization value in response to the fact that the target PCB pressing equipment does not conform to the risk assessment standard. The rejection rate and the energy consumption are reduced through self-adaptive regulation and control.

The application discloses a grounding processing method and system of a printed circuit board, electronic equipment and a storage medium. The printed circuit board is connected with a chip. The grounding processing method comprises the following steps: acquiring the use state of the chip pin between the main ground to be extended and the target grounding area of the printed circuit board; grounding the connection point on the printed circuit board corresponding to the unused chip pin; connecting the grounded connection point into an extended ground wire; and extending the main ground to be extended to the target grounding area through the extended ground wire. According to the grounding processing method, the connection point on the circuit board corresponding to the unused pin of the chip is grounded, and the ground under the chip is connected into the ground wire through the grounded connection point and extended to other areas, so that the area and continuity of the ground under the chip are increased, the impedance between the digital ground and the analog ground in the chip is reduced, the static electricity in the chip is quickly returned to the ground, and the stability of the system is improved.