424 results about "Package design" patented technology

A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

A hermetically sealed, opto-electronic array housing assembly having a ceramic base, electrical connectors, a metal can, and a glass window. The glass window can support a micro-lens array. The metal can receives the glass window. The electrical impedance of the electrical connectors is beneficially carefully controlled to enable high-speed data communications. A multi-element optical fiber connector can provide for optical communications to and/or from an opto-electronic array contained within the housing.

The present invention is a non-destructive method of inspecting a bond, particularly a braze bond, in a hermetic package. The invention involves a unique hermetic package design adapted for ultrasonic inspection and a method of inspecting the package. This package and non-destructive inspection process are particularly useful in implantable neural stimulators such as visual prostheses.

A multigrade engine oil meeting the specifications for SAE J300 revised June 2001 requirements and a process for preparing it, said engine oil comprising (a) between about 15 to about 94.5 wt % of a hydroisomerized distillate Fischer-Tropsch base oil characterized by (i) a kinematic viscosity between about 2.5 and about 8 cSt at 100° C., (ii) at least about 3 wt % of the molecules having cycloparaffin functionality, and (iii) a ratio of weight percent molecules with monocycloparaffin functionality to weight percent of molecules with multicycloparaffin functionality greater than about 15; (b) between about 0.5 to about 20 wt % of a pour point depressing base oil blending component prepared from an hydroisomerized bottoms material having an average degree of branching in the molecules between about 5 and 9 alkyl-branches per 100 carbon atoms and wherein not more than 10 wt % boils below about 900° F.; and (c) between about 5 to about 30 wt % of an additive package designed to meet the specifications for ILSAC GF-3.

The present invention is a novel child-resistant senior-friendly blister card packaging that is cheap and easy to manufacture. The packaging requires a push-peel-push method for opening, which is cognitively and physically challenging for children and mentally impaired adults. Yet, competent adults can easily open the package, especially after reading instructions. More specifically, opening the package requires the user to: 1) Push through an aperture to create a pull tab; 2) Pull on the pull tab to remove a panel; and 3) Push the blister to force the contents through the blister's seal. Furthermore, the packaging is designed to be tear resistant and to halt any propagation of a tear. Advantageously, the present invention is designed such that information such as instructions and product information can be easily printed directly on the packaging. Moreover, users may also record information directly on the packaging. Thus, the present invention not only provides child-resistant and senior-friendly features, but also provides convenience for viewing and recording information.

A computer implemented method to estimate a respondent's or a set of respondents' rank order with respect to a number of attribute options (i.e. alternative prices, features, benefits, ways of expressing benefits, brand names, slogans, logos, graphic treatments such as package design elements and any other stimuli that the researcher believes may influence the individual's opinion such as a statement, graphic or brief audio). The method can be used when the number of stimuli to be presented exceeds the number that can be presented at one time to a respondent, most typically, exceeding the number that can be legibly displayed on one computer screen for rank ordering by a respondent. The estimated rank order is highly accurate, especially for the highest ranked stimuli, but requires only a small fraction of the respondent input that would be needed to capture a complete rank order from that respondent. This abstract is provided as an aid for finding relevant disclosures and not as a limitation on the scope of the claims.

A direct contact cooling liquid embedded package design for use with a computer central processor unit is suitable for thermal management of high heat dissipation electronic components such as server processors. The direct contact cooling liquid embedded packaged CPU has mechanical coupling and embedded plumbing that attaches to the board pumped liquid supply and direct contact cooling liquid of the heat-generating portion of the CPU. A direct contact cooling liquid embedded packaged CPU removes higher levels of heat directly from the core of the processors by convective cooling. Cooling liquid is introduced into the package of the server CPU by mechanically attaching the CPU to the board through a socket interconnect. Pins of the socket serve to provide electrical connection between the board and the CPU, while a few pins are designed for the purpose of inlet and outletting cooling liquid into and out of the CPU package.

A push-button switch includes a universal assembly comprising a single body design, a single plunger design, and a single base design to provide various switch options in an overall single package design. The push-button switch of the invention may be operated by either a mechanical switch assembly or a hall-effect system. The push-button switch may also provide a momentary switch connection, such as a single push system, or a maintained switch connection, such as a push-push system. Further, the push-button switch may include feedback mechanisms, such as LED components and the like that provide a visible feedback of the switch connection, and tactile feedback components that also indicate the switch connection.

The invention discloses a low-cost tunable DFB semiconductor laser device of an integrated modulator. The tunable DFB semiconductor laser device is manufactured with the reconstruction-equivalent chirped technology, multiple DFB semiconductor laser devices share one modulator, and the tunable wavelength range can be expanded by increasing the number of laser devices or adopting the active and passive integration method. The integrated modulator is an semiconductor optical amplifier modulator (SOA), or an electric absorption modulator (EAM), or a Mach-Zehnder modulator (MZM) and can be realized by means of the quantum well intermixing technology (QWI), the Butt-joint growth technology or the selective area growth technology (SAG), and quantum well materials are based on the InP/InGaAsP or InP/AlGaInAs material system. Due to the fact that only one radio frequency port is needed for modulation at least, cost can be reduced by simplifying package design, and practicality and usability are improved greatly.

Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

A method and device of fabricating a photovoltaic strip. The method includes providing a photovoltaic cell having a front surface and a back surface and forming a first grid pattern on the front surface and second grid pattern on the back surface. The first grid pattern includes a first plurality of strip columns in parallel in a first direction and a plurality of grid lines in parallel in a second direction perpendicularly crossing the first plurality of strip columns. The second grid pattern includes a plurality of blocks separated by a plurality of streets parallel in the second direction and a second plurality of strip columns parallel in the first direction. The method further includes dicing the photovoltaic cell along the plurality of streets into a plurality of photovoltaic strips. Each of the plurality of photovoltaic strips includes at least one of the plurality of grid lines.

An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.

A physic package for an atomic clock comprising: a block made of optical glass, a glass ceramic material or another suitable material that includes a plurality of faces on its exterior and a plurality of angled borings that serve as a vacuum chamber cavity, light paths and measurement bores; mirrors fixedly attached using a vacuum tight seal to the exterior of the block at certain locations where two light paths intersect; optically clear windows fixedly attached using a vacuum tight seal to the block's exterior over openings of the measurement bores and at one location where two light paths intersect; and fill tubes fixedly attached using a vacuum tight seal to the exterior of the block over the ends of the vacuum chamber cavity. This physics package design makes possible atomic clocks having reduced size and power consumption and capable of maintaining an ultra-high vacuum without active pumping.

Embodiments in accordance with the present invention relate to packaging designs for vertical conduction semiconductor devices which include low electrical resistance contacts with a top surface of the die. In one embodiment, the low resistance contact may be established by the use of Aluminum ribbon bonding with one side of a leadframe, or with both of opposite sides of a leadframe. In accordance with a particular embodiment, the vertical conduction device may be housed within a Quad Flat No-lead (QFN) package modified for that purpose.

An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and reflect the pin swap in the symbol library, the FPGA information, a circuit diagram, and a constrained condition.