Forming method of metal gate, forming method of MOS transistor and forming method of CMOS structure

Abstract

The invention discloses a forming method of a metal gate, a forming method of an MOS (metal oxide semiconductor) transistor and a forming method of a CMOS (complementary metal oxide semiconductor) structure. The forming method of the metal gate comprises the following steps: after removing a pseudo polycrystalline silicon gate and forming a groove, forming high-K gate medium layers at the bottom and on the side wall of the groove, fluoridizing the high-K gate medium layers, and forming a function layer and a metal layer on the surfaces of the high-K gate medium layers. As fluorine bonds such as fluorine-silicon bonds and fluorine-hafnium bonds can be formed among the high-K gate medium layers and a semiconductor substrate after fluoridization and the bond energy of the fluorine bonds is higher than that of original hydrogen bonds, the instability of the negative bias temperature of a device is reduced; as fluorine is strong in oxidability, oxygen vacancies can be prevented from generating donor level in a band gap and becoming positively charged oxygen vacancies, the oxygen vacancies are passivated, and the instability of the positive bias temperature of the device is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a metal gate, a method for forming a MOS transistor with a corresponding metal gate, and a method for forming a CMOS structure. Background technique [0002] With the continuous development of semiconductor technology, the feature size of MOS transistors is continuously reduced, and the thickness of the gate dielectric layer of MOS transistors is also becoming thinner and thinner according to the principle of proportional reduction. When the thickness of the gate dielectric layer is thin enough to a certain To a certain extent, its reliability issues, especially time-related breakdown, hot carrier effect, diffusion of impurities in the gate electrode to the substrate, etc., will seriously affect the stability and reliability of the device. Now, SiO 2 layer as a gate dielectric layer has reached its physical limit, using a high-K gate dielectric lay...

AI Technical Summary

Problems solved by technology

[0003] However, since the high-K gate dielectric layer is mostly metal ion oxide, and there is no fixed atomic coordination, the bonding between it and the silicon substrate is more stable than that of SiO 2 Compared with the stability of the bonding between the silicon substrate, it is much worse, resulting in a large number of interface defects between the high-K gate dielectric layer and the silicon substrate

Images