Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the steps of providing a semiconductor substrate, wherein a gate groove isformed on the semiconductor substrate; and forming a high-k dielectric layer at the bottom of the gate groove and also comprises the following steps of performing first annealing under an atmosphere containing a hydrogen element before the high-k dielectric layer is formed so that a suspension bond exposed out of the gate groove and in the semiconductor substrate is passivated, and / or performing second annealing after the high-k dielectric layer is formed so that oxygen vacancy in the high-k dielectric layer is passivated. According to the manufacturing method, first annealing is performed under the atmosphere containing the hydrogen element before the high-k dielectric layer is formed so that the exposed suspension bond in the semiconductor substrate is passivated, hot carrier injection (HCI) and negative bias temperature instability (NBTI) of the device are improved, second annealing is performed after the high-k dielectric layer is formed so that the oxygen vacancy in the high-k dielectric layer is passivated, positive bias temperature instability (PBTI) is further improved, and the performance and the reliability of the device are improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, the fabrication of semiconductor devices is limited by various physical limits. [0003] For smaller nanotechnology process nodes, such as 7nm and below nanotechnology process nodes, PMOS devices can use Ge channels, while NMOS devices can use III-V compound semiconductors (such as InGaAs) as channels to increase carrier density. mobility. Due to the continuous shrinking of technology node...

AI Technical Summary

Problems solved by technology

Due to the continuous shrinking of technology nodes, the application of high-k dielectric layer can increase the physical thickness of the gate dielectric film while keeping the gate capacitance unchanged, so as to reduce the leakage current of the gate dielectric layer and improve the reliability of the device. In addition, in order to improve the interface characteristics between the high-k dielectric layer and the substrate, an interfacial layer (IL) is usually formed between the high-k dielectric layer and the substrate. However, using the existing preparation process, the formed There are often many defects such as oxygen hole defects in the high-k dielectric layer. The existence of these defects has great influence on the reliability of the device, for example, hot carrier injection effect HCI (hot carrier injection), negative bias temperature instability ( Negative Bias Temperature Instability, referred to as NBTI), positive bias temperature instability (Positive Bias Temperature Instability, referred to as PBTI) and other negative effects

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