38results about How to "Increase storage window" patented technology

The invention discloses a nonvolatile memory with a multi-layer nanocrystal floating gate structure, which belongs to the technical field of the nonvolatile memory. The nonvolatile memory comprises a semiconductor substrate 11 used for supporting the entire nonvolatile memory, a source 9 and a drain 10 which are formed in the semiconductor substrate 11 in a doped way, a channel 12 between the source 9 and the drain 10, a tunneling oxidizing layer 13 positioned on the channel 12, a control oxidizing layer 14 used for controlling oxidation of the multi-layer nanocrystal floating gate structure, a gate electrode 16 positioned on the control oxidizing layer 14 and a multi-layer nanocrystal floating gate structure 15 positioned between the tunneling oxidizing layer 13 and the control oxidizing layer 14 and used as the floating gate storage unit of the nonvolatile memory. The invention also discloses a method for preparing the nonvolatile memory with the multi-layer nanocrystal floating gate structure. The invention solve the contradiction between the programming time/voltage of the single-layer nanocrystal floating gate memory and the storage time, and increases the storage time of the element under the precondition of shorter programming time.

The invention discloses a memory and a manufacturing method of the memory. The memory structurally comprises a semiconductor substrate, a channel region, a grating stack and a source region or a drain region, wherein the channel region is arranged on the semiconductor substrate; the grating stack is arranged on the channel region and comprises a tunneling layer, a charge trapping layer, a barrier layer and a gate electrode layer; the tunneling layer is arranged on the channel region; the charge trapping layer is arranged on the tunneling layer; the barrier layer is arranged on the charge trapping layer; the gate electrode layer is arranged on the barrier layer; the source region or the drain region is arranged on two sides of the channel region and is embedded in the semiconductor substrate; and the charge trapping layer comprises a first charge trapping layer and a second charge trapping layer(s), wherein the second charge trapping layers which are arranged above or/and below the first charge trapping layer.

The invention discloses a multi-layer floating gate nonvolatile memory structure and a production method thereof, wherein the multi-layer floating gate nonvolatile memory structure comprises a silicon substrate, a silicon dioxide layer, a silicon nanocrystals / high temperature oxide multilayer structure, a polysilicon layer, a silicon dioxide layer, grid and source / drain region formed by sculpturing on the silicon substrate, and a side wall formed by sculpturing on the silicon dioxide layer. The invention solves the defects because the traditional Flash technology node can downsized, utilizes the multi-layer floating gate to storage charge to enhance a storage window, so that the reliability of the floating grid for storing charge can be increased and the retention performance of a floating device can be improved.

The invention aims to provide a multistage resistive random access memory and a manufacturing method of the multistage resistive random access memory. The multistage resistive random access memory comprises a substrate, a bottom electrode, a resistive layer and a top electrode, wherein the substrate, the bottom electrode, the resistive layer and the top electrode are arranged from bottom to top in sequence. The multistage resistive random access memory is characterized in that an isolation layer is further arranged between the bottom electrode and the resistive layer. According to the multistage resistive random access memory and the manufacturing method of the multistage resistive random access memory, the nanoscale isolation layer is additionally arranged, so that the magnitude of a storage window of the resistive random access memory is increased to over 105, and the primary condition needed by multistage storage is met; electrochemical active materials are used as the top electrode, different resistance states are achieved under the condition of different voltage drives through the drifting character of the electrochemical active materials, and the purpose of multistage storage is achieved; in addition, due to the additional arrangement of the isolation layer, dissipation of oxygen ions in the movement process is reduced, the bottom electrode is effectively protected, and the stability of a device is improved. In addition, the manufacturing method of the multistage resistive random access memory is simple and easy to control.

The invention relates to a multiple-valued non-volatile memory and a preparation method thereof. The memory comprises a semiconductor substrate, wherein both ends of the semiconductor substrate include a source electrode and a drain electrode respectively along the direction of a memory bit line and both ends of the semiconductor substrate include a shallow tunnel isolation structure respectively along the direction of a memory sub-line. A tunneling dielectric layer, a charge storage layer, a charge blocking layer, and a gate electrode are sequentially arranged on the semiconductor substrate, wherein the charge storage layer is a combination of two different storage materials which are alternatively arranged along the direction of the memory sub-line. The multiple-valued non-volatile memory of the invention adopts the storage layer formed by alternatively arranging the two different materials, which increases the storage density, promises a large window while reducing the thickness of a gate dielectric layer greatly,. Therefore, multiple-valued storage and high-density storage are realized the cost is reduced in turn.

The present invention provides a programming method of ferro-electric dynamic random memory single-tube unit array, belonging to the field of semiconductor integrated circuit design and manufacture technology. In the course of programming true unit said method can apply the voltage for inhibiting programming to word line, bit line and source line of non-true unit so as to make the range of programming voltage which can be applied to said single-tube unit array be further increased, so that the larger storage window can be obtained.

The invention provides a resistive random access memory and a manufacturing method thereof. According to the resistive random access memory and the manufacturing method thereof provided by the invention, a first electrode is formed on the surface of a semiconductor substrate, an intercalation layer is formed on the first electrode, a resistive switching layer is formed on the intercalation layer,a barrier layer is formed on the resistive switching layer, and a second electrode is formed on the barrier layer. The intercalation layer can be matched with the resistive switching layer to achievebetter device performance, and the initial resistance of the resistive random access memory can be modulated through the intercalation layer, so that the storage window of the resistive random accessmemory can be enlarged, and the process uniformity and the performance of the resistive random access memory can be improved.

The invention provides a device with storage and gating functions which comprises a bottom electrode, a conversion layer and a top electrode sequentially from downside to upside; the bottom electrodeis TiN or conductive glass; the conversion layer is made of niobium oxide; and the top electrode is tungsten. The device with the storage and gating functions is composed of the niobium oxide which serves as the conversion layer, the TiN or conductive glass which serves as the bottom electrode, and the metal tungsten which serves as the top electrode. The experimental results show that the deviceprovided by the invention has a gating function in the presence of big current limitation and has a resistance change performance (storage performance) in the presence of small current limitation; thedevice also has excellent stability as the deviation degree of the obtained curve is very small after the device is subjected to circular test for 100 turns in the gating and resistance change performance test; and the device also has a relatively big storage window as the resistance value of a high-resistance resistor is 10 greater than that of a low-resistance resistor in the resistance changeperformance test.

The invention relates to a memory method for a nanocrystalline floating gate structure-based multi-value nonvolatile memory, and belongs to the technical field of memories. In the memory method, hot electron injection is used as a programming mode, Fowler-Nordheim (FN) tunneling is used as an erasing mode, and four memory states of 00, 01, 10 and 11 are differentiated according to amplitude of read current, so that multi-value memory can be realized under the condition of the same area to double memory capacity. In the method, the new programming mode is adopted to simultaneously program at asource end and a drain end, and the multi-value memory is formed, so that the programming efficiency is greatly improved, a memory window is also increased, memory of more points is realized, and thememory capacity which is twice the conventional memory capacity is realized on a memory unit of the same size; in addition, a manufacturing process is not changed while the advantage is realized, andthe cost is greatly reduced.

The invention discloses a nano tunnel and silver nanoparticle coexisting organic field effect transistor memory and a preparation method thereof. The memory structurally comprises a source and drain electrode, an organic semiconductor layer, a charge storage layer, a gate insulating layer, a substrate and a gate electrode formed on the substrate from top to bottom in sequence, wherein the charge storage layer comprises two layers, the first layer is a polymer layer with a nano tunnel structure, and the second layer is a silver nanoparticle layer uniformly distributed on the polymer layer. The charge storage layer is prepared by adopting a secondary spin-coating solution processing method, the preparation process is simple, and large-area preparation can be realized. The film morphology of the nanopore can be regulated and controlled by simply adjusting the spin-coating rotating speed through primary spin-coating, and then the silver nanoparticles are uniformly distributed on the nanopore morphology through secondary spin-coating. The storage capacity, the high mobility and the switch ratio are achieved, the stability is greatly improved, the price is low, the cost is saved, and popularization and integrated commercial application are facilitated.

The invention discloses a groove-type silicon nanocrystalline memory and a manufacturing method thereof. The groove-type silicon nanocrystalline memory comprises a groove formed in the surface of an etching silicon substrate, a main structure of the silicon nanocrystalline memory formed in the groove, a polysilicon gate covered above the groove of the silicon substrate, and a source electrode and a drain electrode formed in the silicon substrate on two sides of the groove, and the main structure comprises a tunneling oxidation layer, silicon nanocrystalline and an inter-gate oxidation layer sequentially from bottom to top. According to the manufacturing method, the groove-type silicon nanocrystalline memory can be manufactured only by etching the groove on the substrate and manufacturing devices on the groove, so that the method is simple; the manufacturing method is completely compatible with conventional CMOS (complementary metal oxide semiconductor) processes, and the devices are good in storage characteristic and high in reliability and quite suitable for large-scale production and wide application; smiling effect in the process of manufacturing of peripheral devices can be thoroughly avoided from oxidizing the silicon nanocrystalline, so that storage characteristics and the like of the devices are guaranteed.