66results about How to "Good retention properties" patented technology

This invention provides a double-fin channel double-grid multifunction field effect transistor and its preparation method, in which, the field effect transistor has a silicon substrate, the channel is two same fins with rectangular sections to form a double-fin channel, the outside of each is oxygen grid and front grid, the inside of which is tunnel through oxidation layer, a SiN4 trap layer, a block oxidation layer and a back grid to form a double-grid structure, two ends of the double-fin channel is connected with a common n+source and n+drain, the front and back grids are aligned covering little part of the n+source and n+drain, a thick SiO2 insulation layer is set just under the channel and the silicon substrate connected with the n+source and the n+drain to form a structure with the double-fin channel on the insulation layer.

According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply potential (VCC-GND) so as to improve resistance against degradation of hold characteristics. Further, low power consumption can be realized along with the improvement. Additionally, the precharge level is set to a power supply of GND or VCC so as to realize a stable supply of the precharge level. Further, a chip size can be reduced since a power supply circuit for precharge is not needed.

A non-volatile semiconductor memory device is provided, which comprises a memory array comprising memory cells, in which each memory cell is capable of storing data values depending on the voltages thereof, the data values include a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range, and the first data is written in a memory cell of the memory cells, a determination section for determining whether a voltage value of the memory cell is higher or lower than a reference value set between a maximum value and a minimum value of the first voltage range, and a rewrite section for rewriting the first data into the memory cell based on a determination result of the determination section so that a margin between the first voltage range and the second voltage range in the memory cell is enlarged.

The invention provides a fin type channel dual-grid multifunctional field effect transistor and preparing method in metallic oxide semi-conductor field effect transistor technique field of the grand scale integration. The flied effect transistor is based on SOI underlay, the cross section of channel is rectangular fin along the vertical direction of the channel and forms the fin channel; a side of the channel is the grid oxide and the front grip, the other side is the tunnel oxide layer as the silicon nitride trap layer, the barrier oxide layer and the back grip of the charge storage layer and forms dual-grid structure; two edges of the fin channel are connected with the common n+ source and n+ leakage, the front grid aligns the back grid, the n+ source and the n+ leakage are covered less; the device achieves the channel section, the source section and the leakage section on the insulating layer based on SOI underlay. The invention is provided with high-effective MOSFET logical device function, the function of high-speed storage and the function of no condenser type DRAM.

The invention provides a method for preparing a metal oxide thin-film resistive random access memory through plasma processing, wherein the method belongs to the technical field of electronic films and components. The memory comprises the components of a substrate, a lower electrode, a fluorine-doped metal oxide and an upper electrode. According to the method, a relatively novel plasma processing method is utilized for conveniently and controllably preparing a metal oxide resistive random access functional layer with uniform defect distribution. The metal oxide resistive random access functional layer can conveniently and quickly realize switching between formation and switching-off of a conductive channel under the function of an electric field, namely switching between a low-resistance state and a high-resistance state of the device. Furthermore, the method has an ultralow working voltage. The upper electrode is prepared through a mask method, thereby greatly reducing device dimension and improving integration density. Through testing, the metal oxide thin-film resistive random access memory prepared according to the method has excellent performance. In one word, the invention realizes the method for preparing the metal oxide thin-film resistive random access memory with advantages high performance and small dimension, wherein the method has advantages of simple operation, effective controllability, high efficiency and low cost. Furthermore relatively high performance consistency is realized. The method is suitable for batch resistive random access array production in future, and furthermore has good application prospect.

The invention provides an organic material resistance random access memory element and a manufacturing method thereof. The structure of the memory element comprises a lower electrode layer, a resistance random dielectric layer, and an upper electrode layer arranged in sequence from bottom to top. The lower electrode layer is an ITO layer. The resistance random dielectric layer is CH3NH3PbI(3-x)Cl3 layer. The upper electrode layer is an Ag layer or an Al layer. The manufacturing method for the organic material resistance random access memory element comprises: using a sol-gel method to form the CH3NH3PbI(3-x)Cl3 layer on the ITO layer of ITO glass, and then performing annealing treatment, and then using a vacuum evaporation method to deposit Ag or Al upper electrode layer on the CH3NH3PbI(3-x)Cl3 layer, and finally a resistance random access memory element whose heterostructure form is Ag or Al/CH3NH3PbI(3-x)Cl3/ITO is formed. The organic material resistance random access memory element is stable in performance, and has relatively good fatigue resistance and holding property.

The invention discloses a method for grafting sabina chinensis on a platycladus orientalis stock. The method is characterized by including the steps that (1) a healthy sabina chinensis scion is picked; (2) a one-year strong platycladus orientalis seedling is picked as the stock; (3) the two sides of a sabina chinensis branch are cut, one side is long, the other side is short, the branch is of a wedge shape, and the length of the branch is identical to the depth of a notch of the platycladus orientalis; the short side of the cut sabina chinensis branch is inserted in the portion close to platycladus orientalis bark, and the long side is close to a platycladus orientalis wood part; (4) after being grafted, the branch is tied tightly through thin film or jute skin; (5) after grafting, planting is conducted; (6) the branch is cut; (7) fertilizer is applied; (8) normal management is conducted.

The invention relates to a collecting circuit for a direct current bus, which is used for collecting direct current bus voltage of a flyback converter. The collecting circuit for the direct current bus comprises a voltage collecting circuit which is connected to a secondary coil of a transformer of the flyback converter by adopting a forward mode, wherein the voltage collecting circuit comprises a voltage sustaining capacitor, a charge and discharge circuit and a follower circuit. In a forward period of the flyback converter, the charge and discharge circuit charges the voltage sustaining capacitor according to the collected direct current bus voltage, and simultaneously, the voltage sustaining capacitor discharges to realize quick charging and quick discharging and improve the real-time of voltage collection; and in a flyback period of the flyback converter, the charge and discharge circuit stops discharging of the voltage sustaining capacitor, and the voltage sustaining capacitor cannot discharge without a discharge circuit, so that excellent sustaining characteristic can be realized, and the sampling accuracy of sample voltage can be improved.

The present invention relates to a nonvolatile memory, comprising a memory cell array and a controller. The memory cell array comprises a plurality of memory cells. The controller is configured to apply a first programming signal to a first memory cell of the plurality of memory cells; verify whether the threshold voltage of the first memory cell reaches a first threshold voltage or not; when thevoltage of the first memory cell reaches a first threshold voltage, verify whether the threshold voltage of the first memory cell reaches a second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage; and when the threshold voltage of the first memory cell does not reach the second threshold voltage, apply a second programming signal to the first memory cell. The threshold voltage of the memory cell located on the lower boundary of the threshold voltage distribution is improved, so that the distribution of each programming state is narrower, the width of the reading window is increased, and the tolerance of the nonvolatile memory to the reduction of the reading window caused by charge loss is improved.

The invention describes a waste ink absorber for an ink jet recording device, wherein the ink is a non-aqueous ink, including a porous plastic prepared by sinter-molding plastic particles; and an oily solvent impregnated into the porous plastic. The invention also describes an ink jet recording device, wherein the ink is a non-aqueous ink, including a waste ink tank including a waste ink diffusing-chamber and an absorber-retaining chamber, and the waste ink absorber, wherein the waste ink absorber is retained in the absorber-retaining chamber and not the waste ink diffusing-chamber.

The embodiment of the invention discloses a three-dimensional memory and a preparation method thereof, and the method comprises the following steps: providing a laminated structure which comprises a plurality of dielectric layers and sacrificial layers, wherein the dielectric layers and the sacrificial layers are alternately laminated, and a channel through hole CH passing through the laminated structure; forming a pre-storage layer on the side wall of the CH; removing the sacrificial layers, and exposing the pre-storage layer; and oxidizing the pre-storage layer at the position where the sacrificial layers are removed so as to form a barrier layer which is relatively close to the outer side and a storage layer which is relatively close to the inner side along the radial direction of the CH.

The invention relates to a discharge gate mechanism. The mechanism comprises a discharge gate which rests against a discharge hopper port inside a discharge bin, a coupler, an L-shaped connecting lever, an axial supporting device of the L-shaped connecting lever, a drive unit of the L-shaped connecting lever and a sealing member for sealing a connecting part of the parts; the coupler consists of a pin boss and a pin inserted into the same, and is externally provided with a matching sealing rubber sleeve; one arm of the L-shaped connecting lever is connected with the discharge gate by the coupler, and the other arm is provided with a stepped section which hermetically passes through a discharge bin shell and is connected with the drive unit, and the stepped section is sequentially sheathed with a sealing rubber cup, a supporting casing and a retaining ring of the axial supporting device; the sealing rubber cup, the supporting casing and the retaining ring are arranged inside a supporting sleeve, one end of the supporting sleeve is fixedly arranged outside the discharge bin shell, and the other end of the supporting sleeve is fixedly connected with the drive unit; and a sealing ring is arranged between the supporting casing and the supporting sleeve. The discharge gate mechanism has the advantages of good tightness, convenient opening and closing and easy assembly and disassembly for cleaning.

Aluminum hydroxide compound coatings are applied to improve phosphors (60 ) retention properties. In particular, the retention of europium-excited, calcium-substituted barium hexaaluminate phosphors (60) after exposure to high-intensity VUV fluxes was significantly improved.

The present invention aims to provide an alignment film that prevents deterioration due to impurity ions in liquid crystal, and a liquid crystal display using the alignment film. The alignment film 10 of the present invention provides an alignment film composed of a resin composition comprising a polyimide resin or a polyamide resin and a low molecular weight thermosetting resin having a viscosity of 1 to 3000 poise at 25°C. The impurity ions 14 in the liquid crystal 12 are prevented from reaching the pixel electrodes 16 by using the alignment film 10 in which the monomer thermosetting resins are mixed. The liquid crystal display of the present invention provided with this alignment film has improved retention characteristics in a reliability test, and is excellent in operating characteristics even when a liquid crystal with high dielectric anisotropy is used.

The invention discloses a scale inhibition pipe and a production process thereof, wherein the production process includes the following steps: S1, taking a PP and/or PE raw material with super high molecular weight, and sintering the PP and/or PE raw material by semi-melt die pressing to form an outer sleeve filter core; S2, taking a PP and/or PE raw material with super high molecular weight, andsintering the PP and/or PE raw material by semi-melt die pressing to form an inner sleeve filter core; and S3, assembly the outer sleeve filter core and the inner sleeve filter core to form a tube body, then pouring an FOF scale inhibitor between the outer sleeve filter core and the inner sleeve filter core, and sintering by semi-melt die pressing to form the scale inhibition pipe. The scale inhibitor in the whole scale inhibition pipe is distributed more uniformly, and the scale inhibition pipe has good scale inhibition effect by slowly releasing the FOF scale inhibitor and can continuously play a role in inhibiting scale. At the same time, the FOF scale inhibitor cannot change the water quality after entering water, has little influence on the pH of raw water, and is conducive to maintaining the characteristics of raw water.

A memory element and a memory device comprising the same are disclosed. The memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed between the ion source layer and the first electrode, the resistance change layer including a layer which includes tellurium and nitrogen (N) and is in contact with the ion source layer. The retention characteristics of the memory element and the memory device in the invention are maintained satisfactorily and the repetitive operation characteristics are improved.