Three-dimensional semiconductor device and production method of three-dimensional semiconductor device

Abstract

The invention discloses a production method of a three-dimensional semiconductor device. The method comprises following steps of forming a mask layer stack composed of multiple alternate first and second mask layers on a substrate; etching the mask stack to form channel holes, thus exposing the top of the substrate and the side walls of the first and second mask layers; removing one part of the second mask layers to form hollows; conformally forming blocking layer in the channel holes and the hollows; forming storage layers on the blocking layers; selectively etching so as to remove one part of the storage layers; and conformally forming tunneling layers in the channel holes and the hollows. According to the three-dimensional semiconductor device and the production method of the three-dimensional semiconductor device provided by the invention, the transversely diffused accesses are cut off by utilizing separated storage layer structures; and the data hold characteristic is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, a multi-layer stacked structure (for example, multiple ONO structures alternating with oxides and n...

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Problems solved by technology

In addition, the charges accumulated in the storage layer will not only diffuse to the direction of the gate directly corresponding to it, but also further diffuse to the charge storage region corresponding to the adjacent (along the channel distribution direction, that is, the vertical direction) gate, cause unnecessary neutralization between erase holes and program electrons, resulting in figure 2 Larger Vt drift shown in the middle ①+② curve

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