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Memory and manufacturing method thereof

A technology of memory and charge trapping layer, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., and can solve the problem of small size of memory cells

Active Publication Date: 2012-12-05
ZHUHAI CHUANGFEIXIN TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Nowadays, the integration density of non-volatile flash memory is getting higher and higher, and the size of storage cells is getting smaller and smaller. The traditional flash memory structure can no longer meet the needs of the development of storage technology.

Method used

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  • Memory and manufacturing method thereof
  • Memory and manufacturing method thereof
  • Memory and manufacturing method thereof

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Embodiment Construction

[0022] Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

[0023] A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, sizes, and relative positions can be...

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Abstract

The invention discloses a memory and a manufacturing method of the memory. The memory structurally comprises a semiconductor substrate, a channel region, a grating stack and a source region or a drain region, wherein the channel region is arranged on the semiconductor substrate; the grating stack is arranged on the channel region and comprises a tunneling layer, a charge trapping layer, a barrier layer and a gate electrode layer; the tunneling layer is arranged on the channel region; the charge trapping layer is arranged on the tunneling layer; the barrier layer is arranged on the charge trapping layer; the gate electrode layer is arranged on the barrier layer; the source region or the drain region is arranged on two sides of the channel region and is embedded in the semiconductor substrate; and the charge trapping layer comprises a first charge trapping layer and a second charge trapping layer(s), wherein the second charge trapping layers which are arranged above or / and below the first charge trapping layer.

Description

technical field [0001] The present invention relates to a memory and its manufacturing method, in particular to a high-k nanocrystalline memory and its manufacturing method, which improves the storage charge of the memory by introducing a high-k nanocrystalline layer into the upper and lower interfaces of the silicon nitride charge trapping layer Ability. Background technique [0002] With the continuous development of semiconductor process technology, non-volatile memory technology has developed rapidly. Taking the most representative flash memory (Flash Memory) as an example, it has successively experienced floating gate memory, NROM (Nitride Read-Only Memory) and SONOS (Silicon Oxide Nitride Oxide Silicon) memory. Nowadays, the integration density of non-volatile flash memory is getting higher and higher, and the size of storage cells is getting smaller and smaller. The traditional flash memory structure can no longer meet the needs of the development of storage technolo...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L29/51H01L21/8247H01L21/28
Inventor 许高博徐秋霞
Owner ZHUHAI CHUANGFEIXIN TECH CO LTD
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