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Erasure method for memory unit

A storage unit, consistent technology, applied in the storage field, can solve the problems of data changes, easy to run out of the capture layer, data can not be well maintained, etc.

Active Publication Date: 2016-05-04
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the inhomogeneity of the charge captured by the shallow and deep storage layers during programming and erasing, the electrons captured by the shallow storage layer will Due to its own movement or other interference, it is easy to run out of the capture layer, resulting in changes in the programmed data, so that the data cannot be kept well

Method used

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  • Erasure method for memory unit
  • Erasure method for memory unit
  • Erasure method for memory unit

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Experimental program
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Embodiment 1

[0023] image 3 It is a flow chart of a method for erasing a storage unit provided by Embodiment 1 of the present invention. This embodiment is applicable to situations where it is necessary to improve the data retention characteristics of the storage unit. join image 3 The erasing method of the storage unit provided in this embodiment specifically includes the following steps:

[0024] S1. Receive programming operation instructions;

[0025] S2. Selecting a memory cell, the word line and the bit line of the selected memory cell are connected to the first programming voltage, the word lines of the unselected memory cell are suspended, and the bit line is connected to a voltage source;

[0026] The above operation may specifically be selecting the storage unit by the address of the storage unit in the programming operation instruction. The word lines and bit lines of the selected memory cells are connected to the first programming voltage, the word lines of the unselected m...

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PUM

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Abstract

The invention discloses an erasure method for a memory unit. The erasure method is characterized by comprising the steps of S1, receiving a programming operation instruction; S2, selecting a memory unit, connecting a word line and a bit line of the selected memory unit to a first programming voltage, suspending a word line of an unselected memory unit, and connecting a bit line of the unselected memory unit to a voltage source; S3, applying a programming pulse to the selected memory unit; S4, applying an erasure voltage pulse to a well CWELL of the selected memory unit; and S5, performing programming verification, and if the verification succeeds, then ending the programming operation, otherwise, performing the step S2. According to the erasure method for the memory unit, provided by an embodiment of the invention, the erasure pulse is applied to the well of the memory unit after the memory unit is programmed each time, so that electrons captured on a surface layer of the memory unit can be erased and the data retention property of the memory unit can be enhanced.

Description

technical field [0001] The embodiment of the present invention relates to the field of storage technologies, and in particular to a method for erasing a storage unit. Background technique [0002] Non-volatile flash memory (norflash / nandflash) is a very common memory chip, which has the advantages of RAM (Ramdom Access Memory, RAM) and read-only memory (ReadOnly Memory, ROM). Data will not be lost when power is off. It is a memory that can be electrically erased and written in the system, and its high integration and low cost make it the mainstream of the market. The Flash chip is composed of thousands of internal storage units, each storage unit stores one bit of data, multiple storage units form a page, and multiple pages form a block. It is precisely because of this special physical structure that in norflash / nandflash Data is read and written in units of pages, and data is erased in units of blocks. [0003] At present, the mainstream 3DN and Flash are all I-type struc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/16G11C16/08G11C16/24G11C16/34
CPCG11C16/08G11C16/16G11C16/24G11C16/3472
Inventor 刘会娟
Owner GIGADEVICE SEMICON (BEIJING) INC
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