13 results about "Electron capture" patented technology

The application relates to a field effect transistor and a power electronic system. The field effect transistor comprises a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a two-dimensional electron gas channel formed between the barrier layer and the channel layer, a source electrode, a gate electrode and a drain electrode formed on the barrier layer and arranged in sequence at intervals along a first direction, a P-type compensation island at least partially higher than the barrier layer and located between the gate electrode and the drain electrode, the P-type compensation island being spaced apart from the drain electrode and the gate electrode, a shielding plate located above the P-type compensation island, a passivation layer arranged between the shielding plate and the P-type compensation island, and the shielding plate being arranged at intervals from the gate electrode and the drain electrode. Through the coupling effect of the P-type compensation island and the shielding plate, the potential distribution between the gate electrode and the drain electrode is more uniform, thereby reducing the peak value of the high field on the drain side, improving the breakdown margin, and effectively reducing the virtual gate effect caused by electron capture after high-voltage turn-off, thereby greatly reducing the increase of the dynamic on-resistance.

The application discloses a wound dressing and a preparation method and application thereof; the wound dressing comprises polymer flexible fibers and cobalt-iron layered double hydroxide nanosheets dispersed in the polymer flexible fibers; the cobalt-iron layered double hydroxide nanosheets contain a cobalt vacancy structure in a crystal lattice. The wound dressing has a strong "electron capture effect" due to the cobalt vacancy. The wound dressing can physically capture electrons on a respiratory transmission chain of a pathogenic bacterial cell membrane, interferes with transmembrane proton transfer and ATP synthesis, directly kills the bacteria through "metabolic starvation", and further has a broad-spectrum physical bactericidal function independent of antibiotics. The wound dressing has excellent superoxide dismutase-like and catalase-like activities, can long-acting capture and remove active oxygen such as superoxide anions and hydrogen peroxide in an inflammatory microenvironment of a wound, promotes macrophages to polarize to a M2 phenotype for promoting repair, and has anti-inflammatory and pro-angiogenic functions.

The application relates to the technical field of piezoelectric photocatalytic materials, in particular to a Na,Sm-CaBi2Nb2O9 / O V -BiOBr piezoelectric photocatalytic material, a preparation method and application thereof. The method comprises the following steps: firstly, preparing Na,Sm-CaBi2Nb2O9 by a molten salt method and dispersing the Na,Sm-CaBi2Nb2O9 in a mannitol solution; then, adding PVP and Bi(NO3)3.5H2O in sequence; and finally, adding a saturated NaBr solution drop by drop and performing hydrothermal treatment; through accurate control of a hydrothermal temperature and a reaction time, a Na,Sm-CaBi2Nb2O9 / O 2+ -BiOBr S-type heterojunction piezoelectric photocatalyst which is rich in oxygen vacancies and has a shared (Bi2O2) V interface is finally obtained. The catalyst realizes the transfer of carrier recombination centers through the electron capture effect of oxygen vacancies, optimizes the local dipole state distribution and the interface non-centrosymmetry, effectively controls the carrier recombination path, significantly enhances the piezoelectric polarization strength, successfully inhibits the self-reduction behavior of the interface Bi 3+ , and greatly improves the piezoelectric photocatalytic activity. The application effectively solves the problems of high crystal face mismatch degree, insufficient stability and low piezoelectric photocatalytic activity of traditional bismuth-based heterojunction materials by constructing structure-matched heterojunction materials, and opens up a new way for the application of layered bismuth-based perovskite materials in the field of piezoelectric photocatalytic water splitting.

A 3D NAND flash memory device and fabricating method thereof, comprises: First, a semiconductor substrate layer is provided, wherein cell isolation structures, channel structures and source lead-out spaces are formed on the semiconductor substrate layer, with the cell isolation structures including cell isolation layers and memory cell-occupied spaces. First dielectric layers and second dielectric layers are sequentially deposited, the first dielectric layer covering at least an exposed surface of the cell isolation structure. The second dielectric layers are then etched to remove all of the second dielectric layers on the side surface and at least part of the second dielectric layers on the second surface, and all of the second dielectric layers on the first surface is retained, with the remaining second dielectric layer forming at least one electron capture layer for memory cell structures. The memory cell structures and electrode structures for the flash memory device are finally fabricated.

The invention discloses a method for analyzing chlorinated paraffin in an environment or food sample. Comprehensive two-dimensional gas chromatography-electron capture negative chemical ion source quadrupole mass spectrometry is used for analyzing short-chain and medium-chain chlorinated paraffin in an environment or a food sample. According to the technology, co-outflow components in a complex matrix can be effectively distinguished through orthogonal separation in a unit mass resolution mode, and characteristic ion response information of a target chlorinated paraffin homologue group (C10-C17) can be rapidly and accurately obtained. The detection limit of the method can reach a nanogram / gram (ng / g) level, and the method has high sensitivity, accuracy and precision; according to the method, the conventional C10-C17 chlorinated paraffin in the environment or food sample can be comprehensively covered and accurately quantified, and the actual demand on comprehensive analysis of short-chain and medium-chain chlorinated paraffin in the current environment and food monitoring is effectively met.

The invention relates to a ferroelectric heterojunction transistor for neuromorphic calculation and a preparation method thereof. The transistor sequentially comprises a gate electrode, a dielectric layer, a ferroelectric layer, a semiconductor layer, a source electrode and a drain electrode from bottom to top, the ferroelectric layer is an organic-inorganic hybrid ferroelectric perovskite material with electron capture sites, and the semiconductor is a two-dimensional bipolar semiconductor material. According to the invention, through heterogeneous integration of the organic-inorganic hybrid ferroelectric perovskite and the bipolar two-dimensional semiconductor material, controllable conversion between ferroelectric polarization and a charge capture mechanism is realized, so that switching between non-volatile storage and volatile synapse weight updating is realized, and the recognition precision and training efficiency of neuromorphic calculation are improved.

The invention belongs to the technical field of catalyst preparation, and particularly relates to a sulfur vacancy Co3O4 / CdIn2S4-Vs composite material as well as a preparation method and application thereof. The method comprises the following steps: putting a CdIn2S4 nano material into an H2O2 solution, stirring, washing and drying to obtain a CdIn2S4-Vs nano material with S vacancy; and then placing the precursor and Co3O4 in absolute ethyl alcohol, stirring, washing and drying to obtain the Co3O4 / Co3O4 composite material. CdIn2S4 is etched through H2O2, CIS-Vs with surface sulfur vacancies are constructed, the surface sulfur vacancies play a role of an electron capture trap, rapid transfer of photo-induced electrons of CdIn2S4 is promoted, and therefore the separation efficiency of photo-induced carriers is remarkably improved. The optimal photocatalytic hydrogen production rate of the composite material reaches 10.378 mmol h <-1 > g <-1 > and is 43 times that of pure CdIn2S4, and the performance of the composite material can still be kept at 93% after a cyclic experiment.

A semiconductor device includes an image sensor device including a capacitor structure including an amorphous component as a dielectric material, the amorphous component including a metal oxide mixture. The amorphous component replaces a crystalline metal oxide dielectric layer stack used in other methods. The amorphous composition reduces or prevents interface defects and electron capture compared to a crystalline metal oxide dielectric layer stack. The single amorphous layer avoids interface between metal oxides and crystal defects of the metal oxides, in which electron capture is readily formed. The resulting image sensor components exhibit reduced latency compared to other methods using crystalline metal oxide dielectric layer stacks. Further, using a single amorphous layer comprising a metal oxide mixture increases the capacitance of the corresponding capacitive structure compared to other methods using a crystalline metal oxide dielectric layer stack.

The application discloses a perovskite solar cell based on electronic interception stable surface passivation layer and a preparation method thereof, and belongs to the technical field of solar cells. The solar cell comprises a transparent conductive substrate, a hole transport layer, a perovskite layer, a surface passivation layer, an electron transport layer and an electrode which are arranged in a stack. The surface passivation layer is made of 3-carbamoyl-2,2,5,5-tetramethylpyrrolin-1-oxyl radical (CTPL) and phenethylammonium chloride. The application introduces CTPL into the phenethylammonium chloride passivation system, captures the photo-generated electrons on the perovskite surface, prevents the photo-generated electrons from generating superoxide radicals with oxygen, thereby inhibits the deprotonation process of the phenethylammonium salt passivation layer, and significantly improves the stability of the passivation layer. Meanwhile, the application avoids the carrier transport obstruction caused by the discontinuous electron capture or interface charge accumulation, maintains the continuity of the charge transport between the absorption layer and the transport layer and the interface matching, and keeps a high photoelectric conversion efficiency and photo-thermal stability in long-term operation.

The invention provides a tungsten oxide loaded ruthenium oxide catalyst, a preparation method thereof and an application in thermoelectric catalytic synthesis of ammonia, the catalyst comprises an oxygen vacancy-rich WO3-x carrier and a RuO2 nanoparticle active component, RuO2 is anchored through oxygen vacancies in the WO3-x carrier to form a Ru-O-W interface structure, and the mass fraction of RuO2 in the catalyst is 0.05 wt.%-5wt.%. The WO3x carrier is impregnated with ruthenium salt, and high-temperature annealing treatment is performed under inert atmosphere protection. The active component Ru is firmly anchored through the electron capture effect of oxygen vacancies, and migration and agglomeration of metal nanoparticles in a high-temperature environment can be effectively inhibited through formed strong interface interaction; and meanwhile, by combining a high-temperature and high-pressure electrochemical reaction system, the solubility and activity of nitrogen in the electrolyte are remarkably improved. Under the conditions of high temperature and high pressure, the ammonia production rate reaches up to 319.45 mu gmg1h1, the Faraday efficiency is 15.53%, and the composite material has excellent structural stability and catalytic activity and provides a new technical approach for efficient electrocatalytic synthesis of ammonia.

To provide a semiconductor device suitable for high reliability and high-speed operation.SOLUTION: A semiconductor device comprising: a first conductor; a second conductor; a first insulator; a second insulator; a third insulator; a semiconductor; and an electron trap layer, wherein the semiconductor comprises a channel formation region, and wherein the electron trap layer comprises a region overlapping with the channel formation region with the second insulator therebetween, A semiconductor device comprising: a first conductor; a second conductor; a first insulator; a second insulator; a third insulator; a semiconductor; and an electron trap layer, wherein the semiconductor comprises a channel formation region, and wherein the electron trap layer comprises a region overlapping with the channel formation region with the third insulator therebetween, wherein the second conductor does not include a region overlapping with the channel formation region.SELECTED DRAWING: Figure 5

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the steps of forming a first electrode layer; forming a first liner layer on the first electrode layer; forming a capacitor dielectric layer on the first lining layer; forming a second lining layer on the capacitor dielectric layer; forming a second electrode layer on the second lining layer; wherein a first electron capture layer is formed in the top area in the first lining layer, and a second electron capture layer is formed in the bottom area in the second lining layer, so that interface electrons at the interface of the first lining layer and the capacitor dielectric layer and interface electrons at the interface of the second lining layer and the capacitor dielectric layer are captured. According to the manufacturing method of the semiconductor device, interface electrons formed at the interface of the lining layer and the capacitor dielectric layer are eliminated through the electron capture layer between the lining layer and the capacitor dielectric layer, the imprinting effect of the semiconductor device is reduced, the reliability of the semiconductor device is improved, and the storage performance of the semiconductor device is improved.