48 results about "Electron capture" patented technology

The invention discloses a gate dielectric film growth process, an HEMT (High Electron Mobility Transistor) device and a preparation method, and the gate dielectric film growth process comprises the steps: executing a primary process cycle of atomic layer deposition, and forming an amorphous gate dielectric film on the surface of a substrate; after the primary process circulation is completed, in-situ gas plasma treatment is executed, a single crystal gate dielectric film converted from the amorphous gate dielectric film after treatment is obtained, and when the single crystal gate dielectric film is formed between a metal gate and a barrier layer of the HEMT device, the interface state of the metal gate at a gate groove can be improved, the quality of a contact interface below gate metal is improved, and the performance of the HEMT device is improved. And the defect density and the electron trapping effect are reduced, so that the problems of serious influence on safe operation of the device and even grid degradation caused by grid leakage and threshold voltage drift after stress of the device can be effectively avoided, and the performance of the device is improved.

The invention relates to a photoelectric device for generating electric energy through conversion of ultraviolet light and near-infrared light, and discloses an ultraviolet photoelectric synapse / near-infrared photoelectric detection dual-mode photoelectric device. The dual-mode photoelectric device integrates dual functions of ultraviolet photoelectric synapse and near-infrared photoelectric detection: the ultraviolet photoelectric synapse function is realized based on a heterojunction formed by a single-layer graphene film and a wide bandgap perovskite Cs3Cu2I5 film, and B4PyMPM is doped in the Cs3Cu2I5 film to serve as an electron capture site, so that the electron capture capability is enhanced, and the photoelectric detection efficiency is improved. The performance of the ultraviolet photoelectric synapse device can be improved; a near-infrared photoelectric detection function is realized based on a heterojunction formed by a single-layer graphene thin film and n-type Ge, and the thickness of the Cs3Cu2I5 thin film is optimized, so that the Cs3Cu2I5 thin film becomes an antireflection layer of a 1550 nm near-infrared band, and the responsivity, the specific detection rate and other properties of a near-infrared photoelectric detection device are improved. The device disclosed by the invention is simple in structure and process, expensive instruments and equipment are avoided, and the preparation cost of the device is reduced.

The invention relates to the technical field of photocatalysts, in particular to a bismuth-defect bismuth oxybromide-sulfur-defect bismuth sulfide bromide heterojunction and a preparation method and application thereof in photocatalytic CO2 reduction, Bi (NO3) 3.5 H2O, thiourea, cetyltrimethylammonium bromide (CTAB) and the like are used as raw materials, and the VBi-Bi4O5Br2 / VS-Bi19Br3S27 heterojunction is prepared through a two-step hydrothermal method. According to the VBi-Bi4O5Br2 / VS-Bi19Br3S27 heterojunction, bismuth vacancies and sulfur vacancies are introduced, the visible light absorption range of the material is expanded through a proper amount of double vacancies, more electron capture centers are provided, and the separation efficiency of photo-induced electrons and the vacancies is improved, so that the VBi-Bi4O5Br2 / VS-Bi19Br3S27 heterojunction has excellent performance of photocatalytic reduction of CO2, and the preparation method of the VBi-Bi4O5Br2 / VS-Bi19Br3S27 heterojunction is suitable for large-scale production and application of the VBi-Bi4O5Br2 / VS-Bi19Br3S27 heterojunction. CO2 can be reduced into a single product CO, and the photoreduction efficiency of the carbon dioxide can be improved.

The invention belongs to the field of photoelectric devices, and discloses a method for improving the performance of a wide bandgap perovskite heterojunction ultraviolet photoelectric synapse device, the ultraviolet photoelectric synapse device realizes an ultraviolet photoelectric nerve synapse function through a heterojunction formed by a PEDOT: PSS hole transport layer and a wide bandgap perovskite PEA2PbCl4 film, B3PyMPM is doped in the PEA2PbCl4 film as an electron capture site, and the performance of the wide bandgap perovskite heterojunction ultraviolet photoelectric synapse device is improved. The electron trapping capability is enhanced, and the performance of the ultraviolet photoelectric synapse device can be improved. The method is simple in process, expensive instruments and equipment are avoided, and the device preparation cost is reduced.

The invention discloses an enhanced GaN HEMT (High Electron Mobility Transistor) device based on a composite gate and gate terminal expansion and a preparation method thereof, the p-InGaN and p-GaN / p + GaN layer heterojunction polarization effect in the composite gate structure of the enhanced GaN HEMT device can generate two-dimensional hole gas on an interface, and more holes are injected into a channel to be compounded with electrons when high leakage voltage is turned off; the electron concentration of the lower channel layer near the gate is reduced, so that electron capture of the buffer layer on the channel layer is inhibited, the dynamic performance of the device is improved, the reliability of the device is enhanced, the gate terminal expansion structure is utilized to expand the composite gate structure, the off-state electric field distribution of the device is optimized, and the reliability of the device is improved. The electric field peak value of the edge of the gate field plate can be redistributed and weakened, the current collapse effect is effectively restrained, and the preparation method of the device is simple in process and low in cost. According to the scheme, the gate stability and the dynamic performance of the device can be improved, and a reliable device basis is provided for a GaN power system with higher frequency, higher efficiency and higher power density.

Provided are a method for controlling an artificial object, a device for controlling an artificial object, and an artificial object provided with the device for controlling an artificial object, whereby an artificial object is controlled with a high degree of freedom without requiring a special propellant. Provided is a control method for controlling an artificial object (100) in the vicinity of a planet or satellite including the earth located in a cosmic space, the control method accelerating the injection of electrons, increasing the potential of the artificial object (100) compared to a state in which no electron is emitted, promoting the capture of electrons present in the vicinity of the artificial object (100) compared to the state in which no electron is emitted, and increasing the potential of the artificial object (100) in the vicinity of a planet or satellite including the earth located in the cosmic space. The electrons captured by the accelerated injection change the momentum or / and angular momentum of the artificial object (100) by a reaction generated in accordance with the momentum imparted to the electrons after the accelerated injection.

The application provides an AlN / HfO2 interface structure design method and device, comprising: establishing a first interface model of AlN / HfO2; optimizing the interface structure of the first interface model to obtain a preset number of second interface models; wherein the oxygen content in the interface structure corresponding to each second interface model is different; optimizing the interface structure corresponding to each second interface model to obtain an energy value corresponding to each second interface model; calculating the electron capture energy and the hole capture energy corresponding to each second interface model; and determining the interface structure corresponding to a third interface model with high electron capture energy according to the electron capture energy and the hole capture energy. The application determines the interface structure corresponding to the third interface model with high electron capture energy by calculating the electron capture energy and the hole capture energy of the second interface model with different oxygen contents, solves the problem that the interface structure with high electron capture capacity cannot be quickly screened, and causes experimental data to be difficult to analyze and a large amount of time to be wasted.

The present invention relates to a photoelectric device that generates electrical energy by converting ultraviolet and near-infrared light. A dual-mode photoelectric device, ultraviolet photosynapse / near-infrared photodetection, is disclosed. This dual-mode device integrates both ultraviolet photosynapse and near-infrared photodetection functions: The ultraviolet photosynapse function is achieved through a heterojunction consisting of a single-layer graphene film and a wide-bandgap perovskite Cs3Cu2I5 film. The Cs3Cu2I5 film is doped with B4PyMPM as an electron-trapping site to enhance electron-trapping capability, thereby improving the performance of the ultraviolet photosynapse device. The near-infrared photodetection function is achieved through a heterojunction consisting of a single-layer graphene film and n-type Ge. The Cs3Cu2I5 film is optimized in thickness to serve as an antireflection layer in the 1550 nm near-infrared band, thereby improving the responsivity, specific detectivity, and other performance characteristics of the near-infrared photodetection device. The device structure and process of the present invention are simple, avoiding the need for expensive instrumentation and equipment, and reducing device manufacturing costs.

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with a pair of first gate structures; forming an electron trapping layer on the substrate, wherein the electron trapping layer covers the side wall and the top of the first gate structure; at least removing part of the electron trapping layer between the paired first gate structures to expose the surface of the substrate; forming a first source-drain doped region in the exposed substrate between the paired first gate structures; forming a second gate structure above the first source-drain doped region, wherein the second gate structure at least covers the side wall and the surface of the electron trapping layer; and forming a second source-drain doped region in the substrate at one side, far away from the second gate structure, of the first gate structure. By adopting the technical scheme, the storage density can be effectively improved.

The invention discloses a BE-SONOS (Bipolar-Silicon Oxide Nitride Oxide Semiconductor) embedded memory structure. The BE-SONOS embedded memory structure comprises a selection gate, a control gate and a floating gate, the control gate is located on the floating gate, and the floating gate and the control gate are isolated by an insulating dielectric layer; the control gates and the floating gates are divided into a plurality of groups, and the selection gate is of a groove type and is positioned in the substrate between the adjacent control gate and floating gate; channel regions are formed in the substrate on the two sides of the trench-type selection gate; the floating gate is of a composite BE-SONOS multi-layer structure and sequentially comprises a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer from bottom to top. According to the invention, the characteristic that an Si dangling bond in the nitride can capture electrons and holes is utilized, the nitride is used as an electron capture layer, and a floating gate of an existing structure is replaced by a BE-SONOS structure, so that the carrier injection efficiency is relatively improved, fewer masks are used in the manufacturing process, the process time is shortened, and the manufacturing efficiency is improved.

The embodiment of the invention discloses a storage method of a field effect transistor, a readable storage medium and a storage system, and the storage method comprises the steps: firstly applying a positive or negative pulse to a grid electrode of a ferroelectric polarization auxiliary charge trapping field effect transistor, so as to enable the field effect transistor to be in an electron trapping state or a hole trapping state; and writing information in an electron capture state or a hole capture state. On the basis of the application, the situation that a large number of electrons or holes are injected and captured in the pulse process of the grid electrode of the field effect transistor, so that the read threshold voltage drifts is considered, the threshold voltage difference value generated by capturing of the electrons or the holes is used as a storage window, information storage is realized, and the reading efficiency is improved. The memory function is realized by utilizing the phenomenon that electrons or holes induced by ferroelectricity are captured and the part of electrons or holes can be retained in a gate medium for a certain time, and a single-transistor DRAM (Dynamic Random Access Memory) memory device with the size of 4F2 is realized.

The application relates to a field effect transistor and a power electronic system. The field effect transistor comprises a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a two-dimensional electron gas channel formed between the barrier layer and the channel layer, a source electrode, a gate electrode and a drain electrode formed on the barrier layer and arranged in sequence at intervals along a first direction, a P-type compensation island at least partially higher than the barrier layer and located between the gate electrode and the drain electrode, the P-type compensation island being spaced apart from the drain electrode and the gate electrode, a shielding plate located above the P-type compensation island, a passivation layer arranged between the shielding plate and the P-type compensation island, and the shielding plate being arranged at intervals from the gate electrode and the drain electrode. Through the coupling effect of the P-type compensation island and the shielding plate, the potential distribution between the gate electrode and the drain electrode is more uniform, thereby reducing the peak value of the high field on the drain side, improving the breakdown margin, and effectively reducing the virtual gate effect caused by electron capture after high-voltage turn-off, thereby greatly reducing the increase of the dynamic on-resistance.

The application discloses a wound dressing and a preparation method and application thereof; the wound dressing comprises polymer flexible fibers and cobalt-iron layered double hydroxide nanosheets dispersed in the polymer flexible fibers; the cobalt-iron layered double hydroxide nanosheets contain a cobalt vacancy structure in a crystal lattice. The wound dressing has a strong "electron capture effect" due to the cobalt vacancy. The wound dressing can physically capture electrons on a respiratory transmission chain of a pathogenic bacterial cell membrane, interferes with transmembrane proton transfer and ATP synthesis, directly kills the bacteria through "metabolic starvation", and further has a broad-spectrum physical bactericidal function independent of antibiotics. The wound dressing has excellent superoxide dismutase-like and catalase-like activities, can long-acting capture and remove active oxygen such as superoxide anions and hydrogen peroxide in an inflammatory microenvironment of a wound, promotes macrophages to polarize to a M2 phenotype for promoting repair, and has anti-inflammatory and pro-angiogenic functions.

The application relates to the technical field of piezoelectric photocatalytic materials, in particular to a Na,Sm-CaBi2Nb2O9 / O V -BiOBr piezoelectric photocatalytic material, a preparation method and application thereof. The method comprises the following steps: firstly, preparing Na,Sm-CaBi2Nb2O9 by a molten salt method and dispersing the Na,Sm-CaBi2Nb2O9 in a mannitol solution; then, adding PVP and Bi(NO3)3.5H2O in sequence; and finally, adding a saturated NaBr solution drop by drop and performing hydrothermal treatment; through accurate control of a hydrothermal temperature and a reaction time, a Na,Sm-CaBi2Nb2O9 / O 2+ -BiOBr S-type heterojunction piezoelectric photocatalyst which is rich in oxygen vacancies and has a shared (Bi2O2) V interface is finally obtained. The catalyst realizes the transfer of carrier recombination centers through the electron capture effect of oxygen vacancies, optimizes the local dipole state distribution and the interface non-centrosymmetry, effectively controls the carrier recombination path, significantly enhances the piezoelectric polarization strength, successfully inhibits the self-reduction behavior of the interface Bi 3+ , and greatly improves the piezoelectric photocatalytic activity. The application effectively solves the problems of high crystal face mismatch degree, insufficient stability and low piezoelectric photocatalytic activity of traditional bismuth-based heterojunction materials by constructing structure-matched heterojunction materials, and opens up a new way for the application of layered bismuth-based perovskite materials in the field of piezoelectric photocatalytic water splitting.

A 3D NAND flash memory device and fabricating method thereof, comprises: First, a semiconductor substrate layer is provided, wherein cell isolation structures, channel structures and source lead-out spaces are formed on the semiconductor substrate layer, with the cell isolation structures including cell isolation layers and memory cell-occupied spaces. First dielectric layers and second dielectric layers are sequentially deposited, the first dielectric layer covering at least an exposed surface of the cell isolation structure. The second dielectric layers are then etched to remove all of the second dielectric layers on the side surface and at least part of the second dielectric layers on the second surface, and all of the second dielectric layers on the first surface is retained, with the remaining second dielectric layer forming at least one electron capture layer for memory cell structures. The memory cell structures and electrode structures for the flash memory device are finally fabricated.

A 3D NAND flash memory device and fabricating method thereof, comprises: First, a semiconductor substrate layer is provided, wherein cell isolation structures, channel structures and source lead-out spaces are formed on the semiconductor substrate layer, with the cell isolation structures including cell isolation layers and memory cell-occupied spaces. First dielectric layers and second dielectric layers are sequentially deposited, the first dielectric layer covering at least an exposed surface of the cell isolation structure. The second dielectric layers are then etched to remove all of the second dielectric layers on the side surface and at least part of the second dielectric layers on the second surface, and all of the second dielectric layers on the first surface is retained, with the remaining second dielectric layer forming at least one electron capture layer for memory cell structures. The memory cell structures and electrode structures for the flash memory device are finally fabricated.

The invention provides a functionalized cornea stroma lens acellular scaffold as well as a preparation method and application thereof, and belongs to the technical field of biomedical materials. A functional cornea-derived natural extracellular matrix (ECM) scaffold is used as a core, a decellularized freeze-drying technology is combined to prepare a decellularized freeze-dried lens (LDL) convenient to store, and an oxidized heparin interface modification technology is used to enrich active factors through an electron capture principle so as to construct a functional ECM platform. And the safety and effectiveness are evaluated in vivo and in vitro. Research results show that the system has long-term storage capacity and low immunogenicity, can prolong the action duration of a nerve growth factor (NGF), effectively inhibits postoperative inflammation and fibrosis in a rabbit cornea stroma lens transplantation model, supports stroma cell colonization and nerve reinnervation, and remarkably promotes cornea tissue repair and regeneration. The novel functional ECM platform developed by the invention provides a new thought and reference for the ECM stent in the field of cornea regeneration treatment.

The invention discloses a method for analyzing chlorinated paraffin in an environment or food sample. Comprehensive two-dimensional gas chromatography-electron capture negative chemical ion source quadrupole mass spectrometry is used for analyzing short-chain and medium-chain chlorinated paraffin in an environment or a food sample. According to the technology, co-outflow components in a complex matrix can be effectively distinguished through orthogonal separation in a unit mass resolution mode, and characteristic ion response information of a target chlorinated paraffin homologue group (C10-C17) can be rapidly and accurately obtained. The detection limit of the method can reach a nanogram / gram (ng / g) level, and the method has high sensitivity, accuracy and precision; according to the method, the conventional C10-C17 chlorinated paraffin in the environment or food sample can be comprehensively covered and accurately quantified, and the actual demand on comprehensive analysis of short-chain and medium-chain chlorinated paraffin in the current environment and food monitoring is effectively met.

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises, from bottom to top, a semiconductor substrate, a heterojunction structure, a cap layer, a first passivation layer, and a second passivation layer; a groove penetrating through the first passivation layer and the second passivation layer; and a P-type semiconductor layer at least on the inner wall of the groove. After the groove is formed by dry etching the second passivation layer, the first passivation layer can be used for etching endpoint detection to avoid over-etching. The first passivation layer exposed at the groove of the second passivation layer can be removed by wet etching. When the first passivation layer is removed by wet etching, the cap layer has very high stability, so that the cap layer is not damaged after the first passivation layer is removed by wet etching. The undamaged cap layer can effectively reduce the surface defects of the heterojunction structure, so as to reduce the probability of electron capture by defects, achieve weakening of the current collapse effect, and reduce the dynamic on-resistance.

The application discloses a double-gate-based GaN high electron mobility transistor structure and a preparation method thereof. The transistor structure comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a dielectric layer. The dielectric layer is provided with a source trench and a drain trench on two sides thereof, and a gate structure is arranged at a position between the source trench and the drain trench. The gate structure comprises a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric. The structure makes the electric field of the right gate of the transistor adjustable by the left gate under the same gate voltage, and the distribution of the electric field is more uniform, thereby improving the gate leakage. Meanwhile, the change of the left gate is small, the hole escape and the electron capture are reduced, and the dynamic threshold and other problems of the device are improved. Under the premise of losing a certain on-resistance and gate capacitance, the saturated source-drain current of the device is improved, the gate leakage is reduced, and the gate reliability is improved.

The invention provides a Cu-based nanocrystalline alloy strip, which is characterized in that the Cu-based nanocrystalline alloy strip is a Cu-Zr-Al-Gd nanocrystalline alloy strip, and the Cu-Zr-Al-Gd nanocrystalline alloy strip is obtained by taking a corresponding amorphous alloy strip as a precursor and carrying out isothermal annealing treatment under a gas protection condition, the internal organization structure of the amorphous alloy strip is adjusted in the annealing process, and excessive precipitation of the active nano-composite from the surface of the material is inhibited; meanwhile, a structural relaxation process is realized through an annealing process, and various intermetallic compounds form a nanoscale microscopic primary battery due to potential difference, so that the catalytic degradation reaction process is enhanced; and the potential difference of various intermetallic compounds forms the effect of a nanoscale microscopic primary battery, and meanwhile, the grain boundary is reduced due to grain growth, so that electron capture can be greatly weakened, electron transport in the material is further promoted, and the catalytic activity is improved.

The application discloses a kind of Mn 0.5 Cd 0.5 Preparation method of S / CaTiO3 / Ni3C material and its application in photocatalytic nitrogen fixation, belong to the technical field of photocatalytic material. First, Mn 0.5 Cd 0.5 S / CaTiO3 S type heterostructure is prepared by in-situ deposition method, then the metalloid Ni3C nano-particle cocatalyst is combined with Mn 0.5 Cd 0.5 S / CaTiO3 by ultrasonic method to form Mn 0.5 Cd 0.5 S / CaTiO3 / Ni3C ternary composite photocatalyst. In the application, semiconductor Mn 0.5 Cd 0.5 S and semiconductor CaTiO3 first form S type heterostructure, not only accelerate the directional movement and separation of photo-generated electrons and holes, but also maintain the strong oxidation-reduction ability of photo-generated charge carriers. In addition, on the basis of S type heterostructure, load Ni3C cocatalyst, Ni3C nano-particle cocatalyst as electron capture center can not only provide more active sites, but also further improve the separation efficiency of charge.

The application relates to a low SET and RESET transient power resistive change memory and a preparation method thereof, which comprises a substrate layer (Si / SiO2), an adhesion layer (Ti), a bottom electrode layer (Pt), a current-limiting layer (SiO2), a resistive change layer (TaON) and an upper electrode layer (TiN) which are sequentially stacked. The application provides a low SET and RESET transient power resistive change memory with a TiN / TaON / SiO2 / Pt structure. The SiO2 prepared by PECVD is used as the current-limiting layer to prevent the resistive change layer from forming thick conductive wires and to prevent large current from being generated. The SiO2 prepared by PECVD contains more defects, and the electrons can be injected into the SiO2 film; the defects in the SiO2 film can be used as traps to capture the electrons; and with the gradual enhancement of the applied electric field, the electrons captured by the traps jump to participate in conduction.

The invention relates to the technical field of luminescent materials, in particular to Sm-doped strontium stannate red and orange fluorescent powder as well as a preparation method and application thereof. The general chemical formula of the red-orange fluorescent powder is Sr2-xSnO4: xSm < 3 + >, wherein x is greater than or equal to 0.001 and less than or equal to 0.01. According to the invention, Sm < 3 + > is introduced and doped in the crystal in high-temperature synthesis to form a point defect energy level capable of storing excitation energy, and the dynamic process of trapping and releasing electrons by traps is regulated and controlled under the combined action of illumination and thermal excitation, so that the temperature enhancement characteristic of Sm < 3 + > luminescence is realized. The fluorescent powder shows an obvious luminescence thermal enhancement characteristic in a temperature range of 303-513K. Meanwhile, when the Sm < 3 + >-Eu < 3 + > fluorescent powder is applied to a fluorescent temperature sensor, a high-sensitivity ratio-type fluorescent temperature sensor can be constructed based on the opposite luminous intensity trend of Sm < 3 + > and Eu < 3 + > in a strontium stannate matrix along with temperature change.

The invention provides a method for extracting singlet split (SF) triplet electrons and application of the singlet split (SF) triplet electrons. In the invention, a strategy of capturing SF triplet state electrons by constructing a donor-acceptor system (D-A system) is provided, a tetracene derivative with efficient intramolecular SF properties is selected as an electron donor, and a non-fullerene organic small molecule is used as an electron acceptor. The energy level of donor / acceptor molecules is adjusted through structural modification, and a D-A system is constructed in a liquid phase, so that the purpose that non-fullerene small molecules efficiently capture triplet state electrons of tetracene oligomer SF is successfully achieved. The SF triplet state electron capture is simply and efficiently realized, a solid foundation is laid for the application of the SF material in the fields of photoelectric conversion, photocatalysis and the like, and the SF material has a potential application prospect in the aspect of greatly improving the efficiency of photovoltaic devices.

The application discloses a piezoelectric catalytic material and a preparation method thereof, and particularly relates to the field of piezoelectric catalytic materials, and comprises a flexible piezoelectric base component, a polarization enhancement component, a free radical activation and electron capture component and a film forming component; by constructing a composite system of synergistically enhanced flexible polymer matrix and high polarization functional filler, the piezoelectric catalytic activity of the material is improved, and the response ability to low-frequency mechanical energy is enhanced, so as to solve the problems of the existing inorganic piezoelectric ceramic, such as large brittleness and insufficient flexibility, and the existing PVDF material, such as low natural polarization phase content and weak carrier migration ability, which result in low catalytic efficiency and insufficient energy conversion; the material exhibits excellent mechanical energy to chemical energy conversion ability under the condition of low-frequency water flow and other natural mechanical excitation, and realizes efficient catalytic degradation of organic pollutants, has good environmental adaptability and stability, and can meet the actual application requirements of flexible, durable and self-powered catalytic materials in the fields of green energy recovery and environmental governance.

The invention relates to a ferroelectric heterojunction transistor for neuromorphic calculation and a preparation method thereof. The transistor sequentially comprises a gate electrode, a dielectric layer, a ferroelectric layer, a semiconductor layer, a source electrode and a drain electrode from bottom to top, the ferroelectric layer is an organic-inorganic hybrid ferroelectric perovskite material with electron capture sites, and the semiconductor is a two-dimensional bipolar semiconductor material. According to the invention, through heterogeneous integration of the organic-inorganic hybrid ferroelectric perovskite and the bipolar two-dimensional semiconductor material, controllable conversion between ferroelectric polarization and a charge capture mechanism is realized, so that switching between non-volatile storage and volatile synapse weight updating is realized, and the recognition precision and training efficiency of neuromorphic calculation are improved.

The invention relates to the technical field of piezoelectric electro-catalytic materials, in particular to a Na, Sm-CaBi2Nb2O9 / OV-BiOBr piezoelectric electro-catalytic material as well as a preparation method and application of the Na, Sm-CaBi2Nb2O9 / OV-BiOBr piezoelectric electro-catalytic material. The method comprises the following steps: firstly, preparing Na and Sm-CaBi2Nb2O9 by adopting a molten salt method, dispersing the Na and the Sm-CaBi2Nb2O9 into a mannitol solution, then sequentially adding PVP and Bi (NO3) 3.5 H2O, and dropwise adding a saturated NaBr solution for hydrothermal treatment; the Na, Sm-CaBi2Nb2O9 / OV-BiOBr S type heterojunction piezoelectric photocatalyst which is rich in oxygen vacancies and has a shared (Bi2O2) < 2 + > interface is finally obtained by accurately regulating and controlling the hydrothermal temperature and the reaction time. According to the catalyst, transfer of a carrier recombination center is achieved through the electron capture effect of oxygen vacancies, local dipole state distribution and non-central symmetry of an interface are optimized, and the piezoelectric polarization intensity is remarkably enhanced while a carrier recombination path is effectively regulated and controlled; therefore, the self-reduction behavior of the interface Bi < 3 + > is successfully inhibited, and the piezoelectric electro-catalytic activity is greatly improved. By constructing the heterojunction material with a matched structure, the problems of high crystal face mismatching degree, insufficient stability, relatively low piezoelectric electro-catalytic activity and the like of a traditional bismuth-based heterojunction material are effectively solved, and a new way is opened up for application of the layered bismuth-based perovskite material in the field of piezoelectric electro-catalytic water decomposition.

Electron trap device 1 comprises a cryogenic apparatus 40, a superconducting circuit 10 and a heat bath 60. The superconducting circuit 10 and the heat bath 60 are placed within the cryogenic apparatus 40. This allows the superconducting circuit 10 to operate and the heat bath 60 to be maintained at a constant low temperature, e.g., about 20 mK. The superconducting circuit 10 comprises a cooling resonator 20, a microwave resonator 22 and an electron trap region 50. The superconducting circuit 10 comprises a microstructure in which the opposing electrodes are arranged in a position that is linear symmetrical to the center line through the electron trap region and surrounded by a superconductor, such that the electron trap region 50 comprises a plurality of opposing electrodes.