Delay locked loop circuit for internally correcting duty cycle and duty cycle correction method thereof

Abstract

A delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves the characteristics of a memory device is described. The delay locked loop circuit includes an additional loop for duty cycle correction as well as loops for controlling a rising edge and a falling edge of output signals. Thus, the delay locked loop circuit can internally correct the duty cycle without the use of a phase blender.

Description

BACKGROUND OF THE INVENTION[0001]This application claims the priority of Korean Patent Application No. 2002-60814, filed 5 Oct. 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.[0002]1. Field of the Invention[0003]The present invention relates to a delay locked loop (DLL) circuit, and more particularly, to a DLL for internally correcting a duty cycle and a duty cycle correction method thereof.[0004]2. Description of the Related Art[0005]In data transmission such as between a memory device and a memory controller where data is transmitted after the data is synchronized with a clock signal, bus load and transmission frequency have increased. Thus, it is increasingly important to synchronize the data with the clock signal. That is, the time required to load the data onto the bus in response to the clock signal is compensated for to place the data at edges or centers of the clock signal. Between a phase locked ...

AI Technical Summary

Benefits of technology

[0012]The present invention provides a delay locked loop (DLL) circuit having a duty cycle corrector (DCC) that preferably has a broad range of duty cycle correction, consumes only a small amount of power, has few restrictions on operating frequency, and improves memory device characteristics.

Problems solved by technology

If the duty cycle of an external clock signal ECLK has a ratio of 40 to 60 or a ratio of 60 to 40, the DCC may not perform properly, and power consumption increases, restricting the operating frequency.

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