2 results about "Fast mode" patented technology

Embodiments of the present application provide an instruction processing method, device and related equipment, the method comprises: in slow mode, obtaining an instruction to be executed, the instruction to be executed is an instruction corresponding to an exception triggering instruction execution mode to switch from fast mode to slow mode; based on a first bit width, the instruction to be executed is decoded to determine the corresponding operation information and the address to be accessed, the address to be accessed is used to access target data with a first bit width; based on a second bit width, the address to be accessed is split into multiple sub access addresses, and the sub target data is accessed based on the sub access addresses, and the judgment of whether the access exception is an error suppression exception exists; after all the sub target data corresponding to all the sub access addresses are accessed, the target data formed by the accessed sub target data is executed according to the operation information. The scheme simplifies the instruction processing flow and reduces the instruction overhead.

The embodiment of the invention provides an instruction processing method and device and related equipment, and the method comprises the steps that in a low-speed mode, a to-be-executed instruction is obtained, and the to-be-executed instruction is an instruction corresponding to an exception of triggering an instruction execution mode to be switched from a high-speed mode to the low-speed mode; the instruction to be executed is decoded based on the first bit width, operation information and an address to be accessed corresponding to the instruction to be executed are determined, and the address to be accessed is used for accessing target data with the first bit width; splitting the to-be-accessed address into a plurality of sub-access addresses based on a second bit width, performing access and storage of sub-target data based on the sub-access addresses, and judging whether an access and storage exception is an error suppression exception when the access and storage exception exists; and after the sub-target data corresponding to all the sub-access addresses are accessed and stored, executing corresponding processing on target data formed by the accessed and stored sub-target data according to the operation information. According to the scheme, the instruction processing flow is simplified, and the instruction overhead is reduced.