6 results about "Fast mode" patented technology

The present invention discloses a simulation method, device, and storage medium for a reconfigurable processor system. Among them, for the simulation method of the reconfigurable processor system, the reconfigurable processor includes a reconfigurable processor and external devices, and it includes: determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; in the case where the simulation mode is the fast mode, determining a simulation duration according to the input parameters; and performing simulation on the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to address-based interfaces within the reconfigurable processor system.

Embodiments of the present application provide an instruction processing method, device and related equipment, the method comprises: in slow mode, obtaining an instruction to be executed, the instruction to be executed is an instruction corresponding to an exception triggering instruction execution mode to switch from fast mode to slow mode; based on a first bit width, the instruction to be executed is decoded to determine the corresponding operation information and the address to be accessed, the address to be accessed is used to access target data with a first bit width; based on a second bit width, the address to be accessed is split into multiple sub access addresses, and the sub target data is accessed based on the sub access addresses, and the judgment of whether the access exception is an error suppression exception exists; after all the sub target data corresponding to all the sub access addresses are accessed, the target data formed by the accessed sub target data is executed according to the operation information. The scheme simplifies the instruction processing flow and reduces the instruction overhead.

The invention discloses an inter-frame fast mode selection method, system and device for HEVC and a medium. The method comprises the steps that whether a current prediction unit is in an SKIP mode or a Merge mode is judged according to the absolute difference sum of the current prediction unit and a DCT conversion coefficient; determining an inter-frame first optimal mode of the current prediction unit according to a judgment result; judging whether to skip selection of an intra-frame mode or not based on the coding block mark of the inter-frame first optimal mode; and if the intra-frame mode is not skipped, selecting the mode with the minimum rate-distortion cost value as a second inter-frame optimal mode according to the rate-distortion cost value of the first inter-frame optimal mode and the rate-distortion cost value of the intra-frame mode. The mode decision is realized by fully utilizing the prediction information and the transformation information, and the inter-frame mode selection complexity is effectively reduced.

The embodiment of the invention provides an instruction processing method and device and related equipment, and the method comprises the steps that in a low-speed mode, a to-be-executed instruction is obtained, and the to-be-executed instruction is an instruction corresponding to an exception of triggering an instruction execution mode to be switched from a high-speed mode to the low-speed mode; the instruction to be executed is decoded based on the first bit width, operation information and an address to be accessed corresponding to the instruction to be executed are determined, and the address to be accessed is used for accessing target data with the first bit width; splitting the to-be-accessed address into a plurality of sub-access addresses based on a second bit width, performing access and storage of sub-target data based on the sub-access addresses, and judging whether an access and storage exception is an error suppression exception when the access and storage exception exists; and after the sub-target data corresponding to all the sub-access addresses are accessed and stored, executing corresponding processing on target data formed by the accessed and stored sub-target data according to the operation information. According to the scheme, the instruction processing flow is simplified, and the instruction overhead is reduced.

The invention relates to the field of network security, and discloses a rule matching method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring detection data and a preset fast mode set; screening a fast mode with hit data from the fast mode set as a target fast mode; the hit data is a first type of characters which are the same as the rapid mode and are contained in the detection data; performing rule matching on a first type of rules corresponding to the target rapid mode according to the target detection object to obtain a rule matching result; the target detection object is a detection object to which the hit data belongs in the detection data; the matching result comprises a plurality of first-class rules matched with the target detection object. Therefore, the screened rules and the detection data can have the same first type of characters in the same detection object, so that the first type of rules matched with the target detection object are more easily hit by traffic, and the matched invalid rules can be reduced.

The invention provides a rapid pattern matching method and system based on a pattern string intermediate character and a medium, and belongs to the technical field of software engineering, and the method comprises the steps: obtaining a to-be-matched target string, and determining a pattern string and the intermediate character of the pattern string; searching all characters which are the same as the middle character of the pattern string in the target string, and determining the position of a first character which is the same as the middle character; sequentially comparing the left character and the right character of the middle character of the pattern string with the left character and the right character of the first character which is the same as the middle character found in the target string, if the characters are consistent, successfully matching, otherwise, searching a second character which is the same as the middle character of the pattern string in the target string, and determining the position of the character; comparing the left character and the right character of the character in sequence, and judging whether the matching is successful or not; repeatedly executing until the last character which is the same as the middle character of the pattern string is found in the target string, sequentially comparing the left character with the right character after the position of the last character is determined, if the characters are equal, matching succeeds, and if the characters are different, matching of the target string fails; and outputting the position of the pattern string character in the successfully matched target string. According to the method, the character comparison frequency in the execution process is greatly reduced, the algorithm execution efficiency is improved, and the time complexity of the algorithm is greatly reduced.