Embodiments of the present application provide an instruction
processing method, device and related equipment, the method comprises: in slow mode, obtaining an instruction to be executed, the instruction to be executed is an instruction corresponding to an exception triggering instruction execution mode to switch from
fast mode to slow mode; based on a first bit width, the instruction to be executed is decoded to determine the corresponding operation information and the address to be accessed, the address to be accessed is used to access target data with a first bit width; based on a second bit width, the address to be accessed is split into multiple sub access addresses, and the sub target data is accessed based on the sub access addresses, and the judgment of whether the access exception is an error suppression exception exists; after all the sub target data corresponding to all the sub access addresses are accessed, the target data formed by the accessed sub target data is executed according to the operation information. The scheme simplifies the instruction
processing flow and reduces the instruction overhead.