12results about How to "Shorten lock time" patented technology

The invention provides a time-delay phase-locked loop circuit and a system device.According to the time-delay phase-locked loop circuit, the first time-delay circuit to the (2a + 1) th time-delay circuit and the second time-delay circuit to the (2a + 1) th phase discriminator are additionally arranged on the basis of an original DLL circuit framework (including a first phase discriminator), the first time-delay circuit is arranged between a controllable time-delay chain and a clock buffer circuit, and the second time-delay circuit is arranged between a controllable time-delay chain and a clock buffer circuit; the second to (2a + 1) th delay circuits are cascaded and further delay feedback clock signals output by the copy clock buffer circuit, so that the second to (2a + 1) th delay circuits and the copy clock buffer circuit generate (2a + 1) feedback clock signals, and the first to (2a + 1) th phase discriminators detect the phase relation between the feedback clock signals and external clock signals. The control circuit can quickly judge the moment when the phase difference between the output clock signal and the external clock signal is less than 1C (the 1C is the coarse adjustment unit length of the controllable delay chain) or is less than 2C and 1C respectively according to the detection results of the phase discriminators, so that the locking steps are reduced, the locking time is shortened, and the locking of the DLL circuit is accelerated.

The embodiment of the utility model provides a phase-locked loop circuit, a chip and electronic equipment, the phase-locked loop circuit comprises a phase comparison module, a control module, an oscillation module, a frequency comparison module and a time delay module, the time delay module is connected with the frequency comparison module, and the time delay module is connected with the control module. When the frequency of the feedback clock signal and the frequency of the reference clock signal meet the preset relation for the first time, the delay module outputs a bandwidth adjustment signal used for reducing the loop bandwidth of the phase-locked loop circuit after a first preset time. According to the invention, the locking time corresponding to the hopping of the frequency of the target clock signal near the center frequency of the reference clock signal can be reduced, so that the locking time of the phase-locked loop circuit can be further reduced.

The present invention relates to a frequency locking method based on an integrated phase-locked loop. It belongs to the technical field of frequency hopping communication. The frequency locking method based on the integrated phase-locked loop is implemented based on a locked frequency source circuit. The method is specifically as follows: when the integrated phase-locked loop is configured, the first analog switch and the second analog switch are first switched to the normally open end, the reverse end of the operational amplifier is interconnected with the same-direction end through the first analog switch, the voltages of the two endpoints are the same, the output of the operational amplifier is in a suspended state, and since the input voltage remains unchanged, the output of the operational amplifier maintains the previous state at this time, and the second analog switch directly connects the VT pin of the integrated phase-locked loop to an externally specified tuning voltage, thereby ensuring that the VT pin is controlled during the configuration of the integrated phase-locked loop; when the integrated phase-locked loop is configured, the first analog switch and the second analog switch are switched to the normally closed end, and the loop works normally. The present invention can effectively solve the problem of a long locking time of the integrated PLL when frequency hopping across VCO slices.

The present invention discloses a charge pump phase-locked loop circuit for improving phase noise, including a frequency detector, a charge pump, a voltage-controlled oscillator, a frequency divider and a loop filter; a frequency detector branch composed of a frequency detector is provided, and the frequency detector branch is connected in parallel between the signal input end of the frequency detector and the signal output end of the charge pump; the frequency detector branch converts the frequency difference of the two input signals to obtain a current pulse signal and connects it to the loop filter, so that a zero point is added to the loop transfer function of the charge pump phase-locked loop; thereby changing the phase noise transfer function of each component of the circuit, making the output phase noise smaller and the output signal jitter smaller. Compared with the traditional charge pump phase-locked loop under the same parameters, the output phase noise of the phase-locked loop of the present invention is smaller, and the output signal jitter of 50KHz-10MHz is reduced from 3.98pS of the traditional charge pump phase-locked loop to 2.42pS; while ensuring sufficient phase margin, the loop bandwidth is increased, thereby further suppressing phase noise and reducing locking time.

The invention provides a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof.The sub-sampling phase-locked loop comprises a sub-sampling loop, a frequency locking loop, a loop filter and a voltage-controlled oscillator, and the sub-sampling loop is used for sampling an oscillation signal output by the voltage-controlled oscillator according to a received reference clock signal; a first current signal is output to the loop filter; the frequency locking loop is used for outputting a second current signal to the loop filter according to the received reference clock signal and the first frequency division signal and generating a dead zone control signal; the dead zone control signal is used for adjusting the first current signal or the second current signal; the loop filter is used for receiving the first current signal and the second current signal and outputting an oscillation control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used for generating an oscillation signal according to the oscillation control signal. The sub-sampling phase-locked loop can generate a plurality of dead zone ranges by using the frequency locking loop, so that the locking time of the sub-sampling phase-locked loop is reduced.

The invention discloses a delay search method and system for a delay phase-locked loop, a computer and a medium, and the method comprises the following steps: enabling a signal to activate a finite-state machine, and jumping to a search state; based on the preset configuration of the finite-state machine, linear step length search is carried out in the guard band range to locate a target phase, if the target phase is not found in the guard band range, linear step length search is carried out again after the guard band range is expanded, and when the real-time phase is equal to the target phase, a symbol state is entered; in the symbol state, the slope of real-time phase change is calculated, and symbol matching is verified; and if the symbols are matched, entering a phase-locked state, fixing a real-time delay change value in the phase-locked state, and pulling up a phase-locked loop activation signal. According to the invention, the digital code which is output by the phase discriminator and represents the phase relationship between the reference clock and the input clock can be received, the delay is searched in a linear search mode, the control signal is sent to the delay line, and the clock delay is changed until the clock meeting the requirement is generated.

The utility model discloses an LED screen power supply fitting assembling jig which comprises an end positioning assembly, a side positioning assembly, an upper positioning assembly and an inner pressing assembly, a bottom plate is of a rectangular plate body structure, the long side edge direction of the bottom plate is the Y direction, and the short side edge direction of the bottom plate is the X direction; the end positioning assemblies are arranged at the two ends of the bottom plate in the Y direction. The two sets of side positioning assemblies are arranged at the two ends of the bottom plate correspondingly. To-be-assembled LED power supply accessories are placed in the Y-direction mounting space and the X-direction mounting space, and the LED power supply accessories are pressed and positioned in the Y direction through the end positioning assemblies and pressed and positioned in the X direction through the side positioning assemblies; the two upper positioning assemblies are arranged at the two ends of the bottom plate correspondingly. The inner pressing assembly is arranged on the lower portion of the bottom plate and penetrates through the bottom plate to extend into the LED power source accessory. According to the utility model, the assembling mode that the X direction, the Y direction, the vertical direction and internal pressure positioning and pressing cooperate with one another is adopted, so that high-precision and high-efficiency assembling of LED screen power supply box accessories is realized.

The invention discloses a clock correction method, circuit and device, and the method comprises the steps: carrying out the multi-round correction of a clock according to a distortion offset and a lookup table, and finishing the correction until a correction parameter reaches a locking target value, and the lookup table is used for indicating the corresponding relation of the voltage, the temperature and a calibration correction parameter; and after the correction is finished, determining a correction parameter initial value and an adjustment step length initial value of the next round of correction by utilizing the locking target value and the corresponding calibration correction parameter in the lookup table, and writing the correction parameter initial value and the adjustment step length initial value into the lookup table. According to the scheme, the locking process of clock correction can be accelerated, the clock correction efficiency is improved, and hardware resources are saved.

The invention discloses a phase frequency detector based on capture acceleration and noise suppression dual-mode adaptive switching, and the phase frequency detector employs a duty ratio shaping module to shape a reference signal and a feedback signal, reduces the duty ratio, expands the working range of a capture acceleration mode, and facilitates the reduction of the locking time of a loop. A mode controller is used for detecting the phase difference of a reference shaping signal and a feedback shaping signal, judging a locking state and controlling a reset path to be switched between a capture acceleration mode and a noise suppression mode, a high phase discrimination blind area introduced by the noise suppression mode is eliminated, and the phase discrimination range of the phase frequency detector is expanded. Reset paths adopted by the invention are a capture acceleration path and a noise suppression path, the capture acceleration path adopts an input delay sampling technology, inherent delay of a reset signal during generation and transmission is counteracted, a phase discrimination range is effectively expanded, and a phase discrimination blind area of the phase frequency detector is reduced; the noise suppression path optimizes the time sequence of reset signal generation and expands the loop charging and discharging time.

The application belongs to the field of integrated circuit technology design, and relates to a passive and crystal-free GFSK transmitter chip, which comprises a radio frequency energy collection module, a power management module, a clock recovery module and an open-loop modulation transmitter module, the radio frequency energy collection module is used for wireless power supply, the power management module controls a power switch of the transmitter chip according to a power supply voltage value, when the power switch is opened, the power management module supplies power to the open-loop modulation transmitter module, the clock recovery module provides a reference frequency for the open-loop modulation transmitter module, and the open-loop modulation transmitter module multiplies the reference frequency to a radio frequency frequency required for transmission and transmits a data signal. The transmitter chip has the advantages of low power consumption and small size, is suitable for wireless sensor network nodes, and has strong commercial value.

The application discloses a game scene data processing method and device, a storage medium and a computer device, relates to the technical field of computers, and comprises the following steps: receiving a scene change request of a game player, extracting a change object and first position data and second position data before and after the change object changes in the scene change request; performing first collision detection on the first position data and a first hierarchical structure binary tree formed by a home scene plot to which the game player belongs, to determine a first hierarchical node corresponding to the change object; performing second collision detection on the second position data and a second hierarchical structure binary tree corresponding to the first hierarchical node, wherein the second hierarchical structure binary tree comprises at least one scene object in the home scene plot corresponding to the first hierarchical node; and if the second collision detection result is that there is no collision, changing the change object from a first position under the first position data to a second position under the second position data, and updating the second hierarchical structure binary tree.