231results about How to "High frequency accuracy" patented technology

A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/f_T of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.

The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.

The invention discloses an optical frequency comb multi-section light wave splicing method of a linear frequency sweeping light source with an ultra-wide spectrum range. The optical frequency comb multi-section light wave splicing method comprises the following steps: step 1, realizing multi-wavelength linear frequency sweeping through utilizing linear changes of light frequency along with time of multi-wavelength optical frequency comb light wave output from a single-sideband light modulator, so as to generate continuous light containing a multi-wavelength simultaneous linear frequency sweeping signal; step 2, adjusting a filter bandwidth of a continuous light signal through an electric control tunable filter, so as to enable a central frequency change speed to be the same as a frequency sweeping speed of frequency sweeping light wave; linearly changing the speed of a linear frequency sweeping speed gamma along with time until the central frequency reaches v1+(N-1)delta f and a central frequency initial value is equal to minimum frequency sweeping light frequency, so as to obtain linear frequency sweeping light wave with the ultra-wide spectrum range. Compared with the prior art, influences of laser relaxation vibration can be basically avoided, and the linear frequency sweeping speed with the extra-high speed can be realized; the frequency sweeping light source with high frequency sweeping linearity and high frequency precision is guaranteed.

A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

The invention discloses a quick acquiring method for multi-frequency-point bioelectrical impedance. A multi-frequency-point composite excitation source Vin is realized based on a DDS (direct digital synthesizer) principle by means of FPGA (field-programmable gate array) programming, the composite excitation source Vin is loaded onto reference resistance Rref and to-be-tested organism electric impedance Zx simultaneously, corresponding amplitudes Ampref and Ampx and phase angles Degref and Degx of the Vref and Vx on frequency points can be acquired accurately by reasonably selecting sampling frequency fs and points N of DFT (digital Fourier transform) and by only performing DFT on the Vref and Vx on the several needed frequency points, and further amplitudes of the to-be-tested organism electric impedance Zx on the frequency points are acquired. The quick acquiring method has the advantages of high impedance acquisition accuracy, small operation amount, high anti-jamming capability, short scanning time and the like.

The invention relates to a resistance capacitance type relaxation oscillator employing a half-period pre-charge compensation technology. Pre-charge is carried out in the half idle period in each period by use of a timing capacitor so as to compensate time delay td generated by comparators and a latch register. The resistance capacitance type relaxation oscillator comprises one reference voltage generation circuit, two timing capacitor charge and discharge circuits, two reference voltage switching circuits, the two comparators, the SR latch register, one charge and discharge control logic generation circuit and two output buffers. According to the invention, in the first oscillation period after the rising edge of an oscillator control signal arrives, the oscillator frequency is 1/(2RC+td), and from the second period, the oscillation frequency is frequency 1/(2RC) with the time delay td eliminated. According to the invention, errors introduced in an oscillator period by the time delay td generated by the comparators and the SR latch register are eliminated fundamentally, and the frequency precision of the oscillator is improved.

The invention provides a built-in oscillation circuit. A negative feedback closed loop circuit type is adopted for the built-in oscillation circuit, and a frequency-voltage conversion mode is used for the built-in oscillation circuit, and therefore the built-in oscillation circuit is enabled to be completely integrated in a chip, crystal oscillators needing to be additionally arranged are saved, and process cost is saved. An oscillation frequency generated by an annular oscillator is converted into a feedback voltage and compared with a reference voltage, then compared results are fed back to a control end of the annular oscillator, the frequency of the annular oscillator is changed, the output frequency deviation is compensated, and therefore work frequency with low temperature drift is output by a loop circuit, and output frequency with high precision is generated.

A double-longitudinal-mode laser composite frequency stabilization method and a device based on a thermoelectric cooler belong to the technical field of laser application; the invention proposes a thermoelectric cooler-based double-longitudinal-mode laser composite frequency stabilization method, a laser of the double-longitudinal-mode laser comprises two working modes of a frequency stabilization mode and a frequency locking mode and takes a thermoelectric cooler as a temperature controlling actuator; when the frequency stabilization mode is adopted, A control system takes the power difference of two longitudinal mode light of the laser as a feedback signal, when the frequency locking mode is adopted, the control system takes the frequency difference of a laser output beam and an external high stable reference beam as a feedback signal, and realizes the frequency stabilization of the laser according to the control algorithm; and improves the relative frequency stability of the double-longitudinal-mode laser from 10<-7>-10<-8> to 10<-9>, thus enhancing environmental adaptability of the laser, and greatly expanding application range of the laser.

The invention discloses a device and a method for synchronizing system frequency in a packet transport network, and relates to a packet transport network in optical communication. The system frequency synchronizing device comprises a microcomputer processor, a field programmable gate array (FPGA) processing module, a clock integrated circuit, a packet transport network service disk, a synchronous state byte extracting module, a synchronous state byte generating module, a phase locked loop circuit, an external clock input circuit, a high stable crystal oscillator, a clock distributing circuit, a HDB3 coding module and an external clock output circuit, wherein the FPGA processing module comprises a preceding stage preselector, a priority level control module, a first selector, a second selector and a third selector. By the device and method, the system frequency in the whole packet transport network can be synchronized rapidly, data business package transmission and smooth transition can be carried out rapidly and hierarchically, and the device is flexible and has high reliability.

The application provides an RC oscillator, including a reference voltage generation unit used for generating a reference voltage; a voltage control relaxation oscillation unit including a first constant current source and a first charge-discharge loop and a second charge-discharge loop, wherein the first constant current source is used for alternately charging the first charge-discharge loop to generate a first oscillation signal or a second oscillation signal, the first oscillation signal and the second oscillation signal are superposed to obtain a third oscillation signal, and the first charge-discharge loop and the second charge-discharge loop are symmetrical in structure; an active filter unit used for integrating the reference voltage and the third oscillation signal to obtain a fourth signal; and a voltage control unit used for comparing the fourth signal and the first oscillation signal to generate a fifth signal, or comparing the fourth signal and the second oscillation signal to generate a sixth signal.

The invention discloses a piezoelectric type brake executing mechanism of an electronic mechanical brake system of a vehicle. The piezoelectric type brake executing mechanism comprises a brake caliper body, a shell, a piston, a brake piston component, a return spring, a displacement amplifying mechanism, a piezoelectric element and a friction block. The brake piston component is installed on the brake caliper body in a sliding mode, the piston and the piezoelectric element are arranged in the shell, one side of the piston abuts against the piezoelectric element, the displacement amplifying mechanism is arranged between the other side of the piston and the brake piston component, one end of the return spring abuts against the brake caliper body, and the other end of the return spring abuts against the brake piston component. The displacement amplifying mechanism comprises a displacement amplifying lever, a protrusion point, a fixed hinge, a base and the like, on the basis of the lever principle, the small displacement amount of the piezoelectric element is amplified, and the requirement of the friction block for the movable displacement is met. An electric field value exerted by the piezoelectric element is adjusted to achieve the control over brake force of wheels, and the dynamic response performance and the brake performance of the brake system can be improved.

The invention discloses a phase-locked loop. The phase-locked loop comprises a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, bonding-wire inductor, a buffer, a prescaler and a digital frequency divider, wherein the input end of the phase/frequency detector is connected with the output end of the digital frequency divider and a reference clock; the input end of the charge pump is connected with the output end of the phase/frequency detector; the input end of the loop filter is connected with the output end of the charge pump; the voltage-controlled oscillator uses a resistor as an electro-static discharge guard; the control voltage input end of the voltage-controlled oscillator is connected with the output end of the loop filter; the bonding-wire inductor is connected with the differential output end of the voltage-controlled oscillator; the differential input end of the buffer is connected to the differential output end of the voltage-controlled oscillator; the prescaler is controlled by Gray codes; the differential signal input end of the prescaler is connected with the differential output end of the buffer; the control signal input end of the prescaler is connected with a first output end of a control logic; a signal input end of the digital frequency divider is connected with an output end of the prescaler; and a control input end of the digital frequency divider is connected with a second output end of the control logic. The phase-locked loop provided by the invention has the advantages of high frequency precision and low noise.

A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

A gas cell unit has a gas cell, inside which a gaseous alkali metal atom is sealed, a heater that heats the gas cell. The heater includes a heating resistor including a plurality of band-like portions so as to be parallel to each other. By making the directions of electric current flowing through two band-like portions adjacent to each other opposite to each other, it is possible to mutually offset or alleviate the magnetic fields generated along with the electric conduction to the plurality of band-like portions.

The invention provides an FM and PM signal carrier capturing method applicable to a random modulation degree. The method comprises following steps of firstly, carrying out down-sampling filtering to input digital baseband signals, thus obtaining down-sampled digital baseband signals; then respectively mixing the digital baseband signals with multiple groups of set local carriers, thus realizing frequency spectrum shift of the baseband signals; carrying out FFT conversion to each frequency spectrum shift branch signal; calculating the power of each spectrum line; searching spectrum line peak values region by region; storing searching results; after a plurality of times of searching is finished, carrying out frequency point verification; eliminating noise interferences, thus obtaining true signal spectrum lines; finally carrying out symmetry judgment to the obtained true signal spectrum lines, thus determining a capturing result. According to the method, the frequency resolution is improved through the frequency spectrum shift; the peak values are searched region by region in the whole capturing range according to the frequencies; the true signals are counted through many times of capturing; the weak signals can be searched in a low signal to noise ratio environment; and the method is applicable to FM and PM signal carrier capturing of random modulation degree.

Disclosed is a frequency synthesizer capable of preventing occurrence of a frequency shift upon occurrence of a change in the level of an input to an A/D converter by preventing PLL control from being properly operated. The frequency synthesizer includes a carrier remove (16), an inverse rotational vector multiplier (17), a phase time difference detector (18), an adder (19), a phase difference accumulator (20), a loop filter (21), a parameter output part (25), an amplitude information detector (26), a filter (27), and a multiplier (28) configured by an FPGA. Unlock detection means monitors the value of amplitude information detected by the amplitude information detector (26). When the value lies within a proper range, a lock (synchronization) process is performed under PLL control, whereas when the value is off the proper range, an unlock state in PLL control is detected.

The invention relates to a millimeter wave sensor and an intelligent detector. The millimeter wave sensor includes a signal generator, a transceiver integrated chip, a bandpass filter, an amplifier, an A/D converter and a digital signal processor connected in sequence. Compared with the existing 24/77GHz millimeter wave sensor, the millimeter wave sensor has higher signal frequency, strong beam directivity, strong anti-interference ability, small size and light weight; in addition, it adopts the transceiver integrated chip based on SiGe process Compared with the sensor composed of discrete devices, it has the advantages of simple structure, small size and portability, convenient mass production, and low cost, which greatly improves the adaptability of the sensor and provides strong technical support for the increasingly complex information detection environment in the future.

The invention provides an optical module for atomic oscillator and an atomic oscillator. An optical module for an atomic oscillator by using a quantum interference effect includes a light source part to emit resonant light having two different wavelengths, a gas cell in which an alkali metal atom gas is enclosed and to which the resonant light is irradiated, a light detection part to detect an intensity of the resonant light transmitted through the gas cell, and a gas-flow generation part to generate a flow of the alkali metal atom gas.

Embodiments of clock circuits disclosed herein include a crystal oscillator circuit, an injection oscillator coupled to kick-start the crystal oscillator circuit and a digital frequency calibration circuit coupled to recalibrate the injection oscillator. The crystal oscillator circuit is configured to generate a clock signal at a resonant frequency. The injection oscillator is coupled to supply an oscillation signal at an injection frequency to the crystal oscillator circuit to reduce a start-up time of the crystal oscillator circuit. The digital frequency calibration circuit is coupled to receive the resonant frequency and the injection frequency as inputs, and configured to supply a digital control signal to the injection oscillator to set the injection frequency of the injection oscillator substantially equal to the resonant frequency of the crystal oscillator circuit. Methods are provided herein to recalibrate the injection frequency of an injection oscillator over time, temperature and/or supply voltage.