Frequency synthesizer

Abstract

Disclosed is a frequency synthesizer capable of preventing occurrence of a frequency shift upon occurrence of a change in the level of an input to an A / D converter by preventing PLL control from being properly operated. The frequency synthesizer includes a carrier remove (16), an inverse rotational vector multiplier (17), a phase time difference detector (18), an adder (19), a phase difference accumulator (20), a loop filter (21), a parameter output part (25), an amplitude information detector (26), a filter (27), and a multiplier (28) configured by an FPGA. Unlock detection means monitors the value of amplitude information detected by the amplitude information detector (26). When the value lies within a proper range, a lock (synchronization) process is performed under PLL control, whereas when the value is off the proper range, an unlock state in PLL control is detected.

Description

technical field [0001] The present invention relates to the frequency synthesizer (synthesizer) that can obtain the oscillating output of desired frequency, relate in particular to when the input level to AD (analog · digital) converter changes, can prevent PLL (Phase Locked Loop, phase-locked loop) ) A frequency synthesizer that controls abnormal operation and prevents frequency deviation from occurring. Background technique [0002] A conventional frequency synthesizer will be described with reference to FIG. 2 . FIG. 2 is a block diagram of a conventional frequency synthesizer. [0003] The existing frequency synthesizer is shown in Fig. 2, has VCO (Voltage Controlled Oscillator: voltage controlled oscillator) 1; Frequency divider 2; Reference oscillator circuit 3; A / D (Analogue / Digital, analog / digital) converter 4 ; phase comparator 5 ; digital filter 6 ; D / A (Digital / Analogue, digital / analog) converter 7 ; [0004] The VCO1 is a voltage-controlled oscillator that use...

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Problems solved by technology

[0018] In this way, if the input level to the ADC changes greatly relative to the reference value, there will be a problem of increased frequency error

[0019] In addition, in the above-mentioned Patent Document 1, the PLL circuit actually outputs the information that the lock is released before the lock is released, but the digital phase comparator does not prevent the change of the input level to the A / D converter. frequency offset

[0020] In addition, in the above-mentioned Patent Document 2, the reproduction signal is converted into a digital signal in synchronization with the sampling clock based on the clock reproduced in the phase synchronization loop, and the clock in the sampling value corresponding to the clock pattern (clock pattern) is converted into a digital signal. Compare at least 2 sampling values ​​near the edge of the pattern, count the number of times of the same comparison result, and detect the locked state when the number is greater than or equal to the predetermined threshold, when the comparison result is reversed in the locked state, when the number of the same comparison result is greater than When it is equal to a predetermined threshold value, it is detected as an unlocked state, but this is an input signal that delays the comparison object, and this prior art does not prevent a frequency shift relative to a level change of the input A / D converter.

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