Periodical precomputation and skew compensation circuit and method for delaying locking loop in FPGA chip thereof

Abstract

The invention discloses a periodical precomputation and skew compensation circuit and a method for delaying a locking loop in a FPGA chip of the periodical precomputation and skew compensation circuit. On the basis of an original traditional DLL locking method, the periodical precomputation technology and the skew preprocessing technology are adopted for two-level processing of clock skew in the FPGA chip, and under the conditions that system stability is maintained and hardware expenses are not increased, the clock skew is removed rapidly, and locking is achieved. According to the method, in the phase locking process of a DLL structure, first-level digital logic computes and loads a preprocessed skew value according to periodical information digitized by a phase shift delay link, and then clock locking is completed by means of second-level counting approximation processing based on the preprocessed skew value. By means of the method, locking time can be effectively shortened, the method is particularly suitable for an occasion with a high demand for low-frequency skew compensation, phase locking time within a DLL operating frequency range can be balanced, and FPGA internal clock management performance can be improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, and is used to improve the internal digital clock management method of a Field Programmable Logic Array (FPGA) chip, in particular to an FPGA on-chip delay-locked loop method based on cycle pre-calculation skew compensation and cycle pre-calculation The skew compensation circuit is mainly to propose a new improvement method for the long locking time consumed by the internal DLL of the FPGA chip to remove the clock skew in the clock system, and the existing DLL improvement structure scheme consumes a lot of resources. Background technique [0002] Acronyms and key term definitions [0003] [0004] Clock skew: In a synchronous digital system, the difference in time between clock edges arriving in different spaces; [0005] Clock Skew Compensation: The delay-locked loop circuit is used to introduce some additional delay, so that the introduced delay plus the original clock ske...

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Problems solved by technology

[0029] Purpose of the invention: The present invention is mainly aimed at the problems that the internal DLL of the FPGA chip consumes long locking time to remove the clock skew in the clock system, and the existing DLL improvement structure scheme consumes a lot of resources, etc., and proposes a new cycle-based pre-calculation skew Compensated FPGA on-chip delay locked loop method and a cycle precalculated skew compensation circuit

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