99results about How to "Shortened fall time" patented technology

A driver circuit includes a circuit 200, a transistor 101—1, and a transistor 101—2. A signal is selectively input from the circuit 200 to a gate of the transistor 101—1 and the transistor 101—2, so that the transistor 1011 and the transistor 101—2 are controlled to be on or off. The transistor 101—1 and the transistor 101—2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

The present invention relates to an MCP unit or the like having a structure intended to achieve a desired time response characteristic, without depending on a limitation imposed by a channel diameter of MCP. The MCP unit comprises the MCP for releasing secondary electrons internally multiplied in response to incidence of charged particles, an anode arranged in a position where the secondary electrons reach, and an acceleration electrode arranged between the MCP and the anode. In particular, the acceleration electrode includes a plurality of openings which permit passing of the secondary electrons migrating from the MCP toward the anode. Further, the acceleration electrode is arranged such that the shortest distance B between the acceleration electrode and the anode is longer than the shortest distance A between the MCP and the acceleration electrode. Thus, an FWHM of a detected peak appearing in response to the incidence of the charged particles is remarkably shortened.

It is an object to suppress deterioration in characteristics of a transistor in a driver cricuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on / off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on / off.

A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

The present invention relates to an MCP unit or the like having a structure intended to achieve a desired time response characteristic, without depending on a limitation imposed by a channel diameter of MCP. The MCP unit comprises the MCP for releasing secondary electrons internally multiplied in response to incidence of charged particles, an anode arranged in a position where the secondary electrons reach, and an acceleration electrode arranged between the MCP and the anode. In particular, the acceleration electrode includes a plurality of openings which permit passing of the secondary electrons migrating from the MCP toward the anode. Further, the acceleration electrode is arranged such that the shortest distance B between the acceleration electrode and the anode is longer than the shortest distance A between the MCP and the acceleration electrode. Thus, an FWHM of a detected peak appearing in response to the incidence of the charged particles is remarkably shortened.

A flat display apparatus comprising a shift register array is provided. The shift register array comprises a plurality of shift registers. At least one of these shift registers comprises a shift register unit, a first TFT, and a second TFT. The shift register unit is configured to receive an activation signal and comprises a first output terminal and a second output terminal. The gate of the first TFT is coupled to the first output terminal. The second electrode of the first TFT receives a clock signal. The gate of the second TFT is coupled to the first electrode of the first TFT. The second electrode of the second TFT is coupled to the second electrode of the first TFT. The first electrode of the second TFT is coupled to the second output terminal.

Optically isolated bias control circuit which provides bias current for switching circuits. Invention is amenable to high speed switching control with instantaneously variable pulse widths and duty cycles. Invention can be operated from DC upward in frequency, limited only by the characteristics of the implementing electrical components and electrical interconnections. Complementary embodiments of invention provide high speed operation with minimal electrical charge flow. Solar powered embodiments of invention may be used to control the switching of high power MOSFET-based switching circuits.

The invention mainly discloses an urban rainwater purification method and a hydraulic jump type filter used therein. According to the technical scheme of the invention, the urban rainwater purification method comprises the following steps: collecting rainwater, detecting the rainwater, carrying out sedimentation treatment, carrying out pH value treatment, carrying out aeration treatment, carrying out biological purification, carrying out fine filtration, and storing. The used hydraulic pump type filter comprises a first filter cartridge and a second filter cartridge, a detection cavity is arranged at a water outlet, only after water body is detected to be in line with urban water consumption requirements by virtue of a detection head, the water body is conveyed into a water storage tank, otherwise the water body is conveyed into the first filter cartridge and the second filter cartridge to be filtered again. The urban rainwater purification method disclosed by the invention has the advantages that the rainwater is collected and purified, collection, permeation, purification and utilization of the rainwater in an urban range are realized to the utmost extent under the premise of guaranteeing waterlogging prevention and safety of a city, urban waterlogging stress can be effectively alleviated and reduced, purification efficiency is high, water quality of the treated rainwater is effectively improved, utilization of a rainwater resource is promoted, and sponge urban construction requirements are met.

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell also includes a balance network to match the stray capacitance seen by each voltage cell.

A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON / OFF characteristics are switched according to High / Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON / OFF characteristics are switched according to High / Low of the reset signal.

A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON / OFF characteristics are switched according to High / Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON / OFF characteristics are switched according to High / Low of the reset signal.

In a constant current switching power supply, the current flowing through the load, is feedback-controlled based on the deviation of the detection value (Id) from the target value (Ir), multiplied by a proportional gain (PG), the value of the gain is set to a predetermined value immediately after the load switching element (5) is turned on, and is thereafter gradually reduced with elapse of time. When the current to the load (4) is supplied by a PWM controlled switching circuit (1), the PWM signal is determined based on a product of the deviation and a proportional gain. It is possible to shorten the rise time of a pulsative load current in a situation where the current is relatively large.

A display panel includes a base substrate, a first gate line, a second gate line, first and second gate pads, a data line, a delay compensating line and a first delay compensating transistor. The first gate line extends in a first direction on the base substrate. The second gate line is substantially parallel to the first gate line. The first and second gate pads extend from first terminals of respective first and second gate lines. The data line extends in a second direction which is different from the first direction. The delay compensating line is substantially parallel to the data line. The first delay compensating transistor is electrically connected to the first and second gate lines and to the delay compensating line.

A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also includes a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled.

A boost circuit is arranged to reduce rise and fall times of pulsed power used for pulsed control operation of electric machines. Magnetic energy present in the electric machine at the end of a pulse is extracted by the boost circuit to reduce the pulse fall time. The energy is stored by the boost circuit and then applied at the beginning of a subsequent pulse to reduce the rise time. By reducing rise and fall times compared to not using such a boost circuit, machine efficiency is improved.

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also include a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled. Isolation diodes ensure that a discharge current can bypass inoperable voltage cells.

A level shift circuit that reduces PMOS to NMOS device contention whole decreasing output rise delays. The invention includes a device, comprising: a level shift circuit for shifting a signal at a first voltage at an input node to a second voltage at an output node; a boost circuit, driven by the second voltage, for decreasing a transition time of the signal between the first and second voltage; and a trigger circuit, coupled to an input of the boost circuit, for turning off the boost circuit when the signal at the output node reaches a predetermined voltage level.

The present invention is related to an array substrate for use in a liquid crystal display. The array substrate includes a transparent substrate; a plurality of gate lines arranged over the transparent substrate in a transverse direction; a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions; a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines; a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines; a plurality of pixel electrodes disposed in the plurality of pixel regions; a plurality of first thin-film transistors disposed in the plurality of pixel regions, each first thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel region; a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and a plurality of second thin-film transistors contacting each other and connecting the feed line to the plurality of gate lines.

A light emitting diode driving device for driving an LED includes (i) a driving pulse current generating circuit for generating a driving current for the LED in accordance with a driving pulse signal supplied from outside and (ii) a differentiating circuit for generating a peaking current obtained by differentiating the driving pulse signal. A current that is equal to the sum of the driving current and the peaking current flows to the LED. The light emitting diode driving device further includes a peaking control circuit for controlling the magnitude of the peaking current generated from the differentiating circuit.

A plurality of power supply circuits Z1′ are provided according to a load capacity. The power supply circuits Z1′ have sides connected in parallel on the side of a direct current input Vi and have sides connected in series on the sides of alternating current outputs Ao. A rectifying circuit DC1 is connected via a resonance circuit Z2 across a combined output of the serially connected sides of the power supply circuits Z1′ on the sides of the alternating current outputs Ao. Switching frequencies are simultaneously controlled by a single control signal outputted from a control circuit S1 based on a direct current output voltage detected from the rectifying circuit DC1 through a detection resistor R5.

A power converting apparatus with dynamical driving adjustment includes a rectifying unit, a power factor correction unit, a power conversion unit and a feedback unit. The rectifying unit rectifies an AC input power to generate and transfer a DC power to the power factor correction unit for performing power factor correction. A power factor correction power is generated and transferred to the power conversion unit. The feedback unit is electrically connected to the power conversion unit to form a closed control loop. A PWM driving controller of the power conversion unit performs an adjustment process to control a switching transistor based on a feedback signal from the feedback unit, and the power conversion unit converts the power factor correction power into an output power supplied to an external load. Thus, the margin for electromagnetic interference is increased, and both switching loss and conduction loss are considerably reduced.

A pixel circuit of a display device of the present invention has a drive transistor which serves also as a transistor adapted to control the emission and non-emission periods of an organic EL element or other elements. A final stage buffer in an output circuit of a write scan circuit (WS) has its power supply separated from the power supply of circuit portions of a previous stage. In a first embodiment, a scan signal WS from the write scan circuit is activated instantaneously. In a second embodiment, the trailing edge of the scan signal WS falls slowly. This allows for writing of an input signal voltage in a stable manner.

A display apparatus includes a display panel including left-eye pixels and right-eye pixels, a three-dimensional controller which separates a first image signal into left-eye and right-eye image signals, outputs a second image signal such that the left-eye image signal is applied to the left-eye pixels during a left-eye frame, a black image signal corresponding to a black data is applied to the right-eye pixels during the left-eye frame, the black image signal is applied to the left-eye pixels during a right-eye frame, and the right-eye image signal is applied to the right-eye pixels during the right-eye frame, and an image display controller which controls the second image signal in response to a control signal, where the left-eye pixels are alternately arranged with the right-eye pixels in the unit of two pixels in a first direction and in the unit of a predetermined number of pixels in the second direction.

A driver circuit includes a circuit 200, a transistor 101—1, and a transistor 101—2. A signal is selectively input from the circuit 200 to a gate of the transistor 101—1 and the transistor 101—2, so that the transistor 101—1 and the transistor 101—2 are controlled to be on or off. The transistor 101—1 and the transistor 101—2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.